Semiconductor device for wireless communication

ABSTRACT

Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2010-242257 filed onOct. 28, 2010 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device for wirelesscommunication, and particularly to a technology which is effective whenapplied to a semiconductor device for wireless communication whichimplements an NFC (Near Field Communication) function in a mobile phone.

For example, in Patent Document 1, a non-contact IC card is shown inwhich a rectifying circuit, two demodulating circuits, and a modulatingcircuit are coupled in parallel to the both ends of an antenna coil.Also, in Patent Document 2, a non-contact data storage system is shownwhich can selectively couple a rectifying circuit and a signal receptionnode or a transmission node to an antenna coil.

RELATED ART DOCUMENTS Patent Documents [Patent Document 1]

Japanese Unexamined Patent Publication No. 2000-172806

[Patent Document 2]

Japanese Unexamined Patent Publication No. Hei 5(1993)-298498

SUMMARY

In recent years, in various countries including Japan as arepresentative and also overseas countries, equipment of a mobile phonesystem with an NFC (Near Field Communication) function has beenpromoted. The NFC function embedded in a mobile phone system isperformed in a card mode in which the mobile phone system operates as anIC card (UICC: Universal Integrated Circuit Card) and in a RW mode inwhich the mobile phone system operates as a reader/writer (RW). Wirelesscommunication operations in the card mode and the RW mode areimplemented by a semiconductor chip (called “NFC chip”) for wirelesscommunication embedded in the mobile phone system.

Since the IC card operates by receiving a power supply from a magneticfield outputted from the reader/writer RW, it is basically unnecessaryto mount a battery or the like on the IC card. However, to the NFC chipembedded in the mobile phone system, an external power supply such as abattery is normally indispensable. For example, when the NFC chipoperates in the RW mode, there is no magnetic field inputted from theoutside so that the NFC chip needs to receive a power supply from anexternal power supply. When operating in the card mode also, the NFCchip needs to have multiple functions (the implementation of e.g., aSuica (registered trademark) card and an Edy (registered trademark)card), unlike a typical single-function IC card (e.g., the Suica(registered trademark) card). As a result, with an increase in powerconsumption, the power supply from the magnetic field may beinsufficient. Moreover, when operating in the card mode, the NFC chipneeds to drive another chip (such as a UIM (User Identity Module) chip)in the mobile phone system from the need to maintain the security of themobile phone system or the like. Therefore, even when the NFC chipoperates alone with the power supply from the magnetic field, it may bepossible that the system does not operate.

However, if it is assumed that an external power supply is indispensableeven when the NFC chip operates in the card mode, a problem may arise inthe practical use thereof. For example, when a user of the mobile phonesystem has taken a train using the Suica (registered trademark) functionembedded in the mobile phone system and then the battery of the mobilephone system is exhausted, the user can no longer use the Suica(registered trademark) function and go out a ticket wicket. Besides, asthe NFC function has become more important as a social infrastructure,it has been considered that a system depending on an external powersupply such as a battery has a problem.

To solve such a problem, e.g., an NFC chip compatible with a Low batterymode can be considered. This enables the NFC chip to operate even with avoltage lower than a voltage at which the mobile phone system can nolonger operate. That is, when the battery of the mobile phone system isexhausted and the output voltage of the battery lowers, the systemstops. The mobile phone system performs communication with a basestation even when it is not actually used (for a phone call, anelectronic mail, or the like) and consumes considerable battery power.Therefore, when the system has stopped, further battery powerconsumption is substantially suppressed. By configuring the NFC functionsuch that it is operable even in this state, a battery lifetime inregard to the NFC function can significantly be elongated.

However, when the Low battery mode is used, the battery lifetime inregard to the NFC function can be elongated, but not infinitely, so thata fundamental solution is not provided. Even when the mobile phonesystem has stopped, the voltage of the battery gradually lowers due tobattery power consumption by a leakage current, the self discharge ofthe battery, or the like and, finally, even the Low battery mode cannothandle the situation. Moreover, since the function of a battery (such aslithium battery) used in the mobile phone system as a secondary batteryis impaired if over discharge occurs, when the voltage of the batteryhas lowered until the Low battery mode can no longer handle thesituation, it is necessary to completely cut off the output of thebattery. In this case, two-level threshold voltages are needed, andconsequently the configuration of the mobile phone system may becomplicated.

To prevent this, a system is desired which has provided an NFC chip withthe function of generating power by rectifying input power from anantenna and can be used even when power is not supplied from the batteryof the mobile phone system (a battery-less operation). At this time, asdescribed above, it is necessary for the NFC chip to drive a chip (suchas a UIM chip) other than itself so that, e.g., higher efficiency or thelike is required of the power generating function. FIG. 23 is aschematic view showing an example of a configuration of a semiconductordevice for wireless communication studied as an example on which thepresent invention is based. A semiconductor device (NFC chip) NFCIC′shown in FIG. 23 for wireless communication includes a rectifyingcircuit RECTC′, a reception block RXBK, and a transmission block TXBK′.

The transmission block TXBK′ is coupled to an external antenna ANT viatransmission external terminals Ptp and Ptm and an external impedancematching circuit MACH. The antenna ANT is formed of an inductor, a Qvalue adjusting resistor, and the like. The reception block RXBK iscoupled to the antenna ANT via reception external terminals Prp and Prn,amplitude limiting eternal resistors Rrp and Rrn, and dc cuttingexternal capacitors Crp and Crn. The rectifying circuit RECTC′ iscoupled to the antenna ANT via power input external terminals Pvp andPvn and dc cutting external capacitors Cvp and Cvn. When thesemiconductor device NFCIC′ operates in the RW mode, it operates with abattery (not shown), outputs a transmission signal from the transmissionblock TXBK′ to the antenna ANT, and receives an input signal from theantenna ANT at the reception block RXBK. On the other hand, when thesemiconductor device NFCIC′ operates in the battery-less mode (mode inwhich the semiconductor device NFCIC′ performs a card operation withoutusing the power of the battery), the rectifying circuit RECTC′ generatespower using the input power supplied from the external reader/writer RWto the antenna ANT, and the reception block RXBK and the transmissionblock TXBK′ operate using the power. Specifically, the reception blockRXBK appropriately processes an input signal from the antenna ANT andthereby recognizes an instruction from the external reader/writer RW.When the semiconductor device NFCIC′ performs transmission toward theexternal reader/writer RW, the transmission block TXBK′ modulates a loadbetween the transmission external terminals Ptp and Ptm and causes theexternal reader/writer RW to recognize a change in magnetic field thathas resultantly occurred in the antenna ANT.

However, when a configuration as shown in FIG. 23 is used, there arematters of concern as shown below. First, an increase in the number ofthe external terminals Pvp and Pvn due to the rectifying circuit RECTC′is concerned. Since the terminals are power terminals, they exertsignificant influence on an area increase (cost increase) together withwiring lines in the chip. Next, degradation of power efficiency due topower leakage is concerned. A path from each of the external terminalsPtp and Ptm to the antenna ANT is designed so as to achieve sufficientimpedance matching for a reduction in loss during transmission from thesemiconductor device NFCIC′. A path from the antenna ANT to each of theexternal terminals Pvp and Pvn is also designed so as to achievesufficient impedance matching for a reduction in input power loss.However, if each of the paths is designed to achieve sufficientimpedance matching, in the RW mode, power transmitted from thesemiconductor device NFCIC′ may leak toward the rectifying circuitRECTC′ to probably degrade the efficiency of antenna drivingtransistors. Conversely, in the battery-less mode, the input power fromthe antenna ANT may leak toward the transmission block TXBK′ to probablydegrade the efficiency of rectification.

The present invention has been achieved in view of the foregoing and anobject thereof is to provide a semiconductor device for wirelesscommunication which achieves a reduction in leakage power and allows animprovement in power efficiency. The above and other objects and novelfeatures of the present invention will become apparent from a statementin the present specification and the accompanying drawings.

The following is a brief description of the outline of a representativeembodiment of the invention disclosed in the present application.

A semiconductor device for wireless communication according to thepresent embodiment includes a first terminal serving as an antennacoupling terminal, a p-type first MISFET for pulling up the firstterminal with a first power supply voltage serving as an externalterminal, an n-channel second MISFET for pulling down the first terminalwith a second power supply voltage serving as an external power supply,and a rectifying circuit section coupled to the first terminal. Therectifying circuit section uses an alternating current signal inputtedto the first terminal via an antenna to generate a third power supplyvoltage having a value higher than that of the first power supplyvoltage and higher than that of a higher-potential voltage occurring atthe first terminal when the foregoing alternating current has a maximumamplitude. The third power supply voltage is used as the bulk voltage ofthe first MISFET. As a result, it is possible to prevent rectifyingpower at the first terminal from leaking to a ground power supplyvoltage via a parasitic PNP bipolar transistor in the first MISFET andimprove power efficiency.

Also, in the semiconductor device for wireless communication accordingto the present embodiment, the second MISFET includes a triple wellstructure, and a voltage level at the same potential as that of thesecond power supply voltage is supplied to an n-type semiconductor layerserving as a middle layer in the triple well structure. As a result, itis possible to prevent a current from leaking from the power supply tothe first terminal through a parasitic NPN bipolar transistor in thesecond MISFET and improve power efficiency.

In addition, since this allows the first terminal to be used as each ofan antenna driving terminal and a rectifying terminal, area and costreduction can be achieved compared with the case where the antennadriving terminal and the rectifying terminal are separately provided.Moreover, since there is no power leakage between the individualterminals, power efficiency can be improved.

The following is a brief description of an effect obtained according tothe representative embodiment of the invention disclosed in the presentapplication. That is, in the semiconductor device for wirelesscommunication having each of a reader/writer function and the functionof an IC card or the like, leakage power can be reduced and powerefficiency can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing an example of an overallconfiguration of a semiconductor device for wireless communicationaccording to an embodiment of the present invention;

FIGS. 2( a) to 2(c) are illustrative views showing, in the semiconductordevice for wireless communication of FIG. 1, a problem when a rectifyingsection is simply coupled to antenna driving external terminals;

FIG. 3 is a circuit block diagram showing, in the semiconductor devicefor wireless communication of FIG. 1, an example of a detailedconfiguration of the main portion thereof;

FIGS. 4( a) to 4(c) are illustrative views showing, in the semiconductordevice for wireless communication of FIG. 3, an example of operationthereof during a battery-less mode period;

FIG. 5 is a block diagram showing an example of a configuration of amobile phone system to which the semiconductor device for wirelesscommunication according to the embodiment of the present invention isapplied;

FIG. 6 is a block diagram showing an example of a more detailedconfiguration of the entire semiconductor device for wirelesscommunication of FIG. 1;

FIG. 7 is a block diagram showing, in the semiconductor device forwireless communication of FIG. 6, an example of a detailed configurationof a transmission block thereof;

FIG. 8 is a circuit diagram showing, in the transmission block of FIG.7, an example of a detailed configuration of an antenna driver sectionthereof;

FIG. 9 is a supplementary view of FIG. 8;

FIG. 10 is a circuit diagram showing, in the transmission block of FIG.7, an example of a detailed configuration of an antenna driver drivingsection thereof;

FIGS. 11( a) and 11(b) show an example of operation of the antennadriver driving section of FIG. 10, of which FIG. 11( a) is a waveformchart during a RW mode period and FIG. 11( b) is a waveform chart duringa card mode (battery-less mode) period;

FIG. 12 is a circuit diagram showing, in the transmission block of FIG.7, an example of a detailed configuration of a transmission controlsection thereof;

FIG. 13 is a circuit diagram showing, in the transmission block of FIG.7, an example of a detailed configuration of the rectifying sectionthereof;

FIG. 14 is a circuit diagram showing, in the transmission block of FIG.7, an example of detailed configurations of a rectification regulatorand a rectification regulator driver thereof;

FIG. 15 is an illustrative view showing an example of operation of astart-up circuit in the rectification regulator of FIG. 14;

FIG. 16 is a truth table showing, in the rectification regulator of FIG.14, an example of operation of a logic circuit section thereof;

FIG. 17 is a circuit diagram showing, in the transmission block of FIG.7, an example of a detailed configuration of a clock extracting sectionthereof;

FIGS. 18( a) and 18(b) show a detail of a carrier detecting section inthe transmission block of FIG. 7, of which FIG. 18( a) is a circuitdiagram showing an example of a configuration thereof and FIG. 18( b) isa waveform chart showing an example of operation in FIG. 18( a);

FIG. 19 is a circuit diagram showing, in the transmission block of FIG.7, an example of a detailed configuration of an internal current supplythereof;

FIG. 20 is a circuit diagram showing an example of a detailedconfiguration of a main portion of a power supply controller of FIG. 6;

FIG. 21 is a supplementary view of FIG. 20;

FIG. 22 is another supplementary view of FIG. 20;

FIG. 23 is a schematic view showing an example of a configuration of asemiconductor device for wireless communication studied as an example onwhich the present invention is based; and

FIG. 24 is a circuit diagram showing an example of a configuration of apull-up PMOS transistor studied as a comparative example of FIG. 3.

DETAILED DESCRIPTION

In each of the following embodiments, if necessary for the sake ofconvenience, the embodiment will be described by being divided into aplurality of sections or embodiments. However, they are by no meansirrelevant to each other unless particularly explicitly describedotherwise, and one of the sections or embodiments is variations,details, supplementary explanation, and so forth of part or the whole ofthe others. When the number and the like (including the number,numerical value, amount, range, and the like) of elements are mentionedin the following embodiments, they are not limited to specific numbersunless particularly explicitly described otherwise or unless they areobviously limited to specific numbers in principle. The number and thelike of the elements may be not less than or not more than specificnumbers.

It will be appreciated that, in the following embodiments, thecomponents thereof (including also elements, steps, and the like) arenot necessarily indispensable unless particularly explicitly describedotherwise or unless the components are considered to be obviouslyindispensable in principle. Likewise, if the shapes, positionalrelationships, and the like of the components and the like are referredto in the following embodiments, the shapes and the like are assumed toinclude those substantially proximate or similar thereto unlessparticularly explicitly described otherwise or unless it can beconsidered that they obviously do not in principle. The same shall applyin regard to the foregoing numerical value and range.

Circuit elements forming each of functional blocks of the embodimentsare not particularly limited, but are formed over a semiconductorsubstrate of monocrystalline silicon or the like by an integratedcircuit technology such a known CMOS (complementary MOS transistor)technology. In the embodiments, as an example of a MISFET (MetalInsulator Semiconductor Field Effect Transistor), a MOSFET (Metal OxideSemiconductor Field Effect Transistor) (abbreviated as MOS transistor)is used, but it is not intended to exclude a non-oxide film fromexamples of a gate insulating film.

Referring to the drawings, the embodiments of the present invention willbe described below in detail. Note that, throughout all the drawings forillustrating the embodiments, like members are designated by likereference numerals in principle, and a repeated description thereof isomitted.

<Schematic Configuration of Entire NFC Chip>

FIG. 1 is a schematic view showing an example of an overallconfiguration of a semiconductor device for wireless communicationaccording to an embodiment of the present invention. A semiconductordevice (NFC chip) NFCIC for wireless communication shown in FIG. 1 isconfigured to include a transmission block TXBK, a reception block RXBK,and a rectifying section RECT provided in the transmission block TXBK.The transmission block TXBK is coupled to an external antenna ANT viatransmission (antenna driving) external terminals Ptp and Ptm and anexternal impedance matching circuit MACH. The antenna ANT includes aninductor, a Q value adjusting resistor, and the like. The receptionblock RXBK is coupled to the antenna ANT via reception externalterminals Prp and Prn, amplitude limiting external resistors Rrp andRrn, and dc cutting external capacitors Crp and Crn. The semiconductordevice NFCIC has a RW mode in which it operates as a reader/writer RWusing the power of a battery (not shown), and a card mode and abattery-less mode in each of which it operates as an IC card. In thecard mode, the power of the battery is used while, in the battery-lessmode, the power of the battery is not used.

The transmission block TXBK includes the rectifying section RECT and anantenna driver section ADRV. During writing (during transmission) in theRW mode, the antenna driver ADRV in the transmission block TXBK outputstransmission signals (tp and tm) toward the transmission externalterminals Ptp and Ptm, which are outputted from the antenna ANT via theimpedance matching circuit MACH. During reading (during reception) inthe RW mode, input signals (return signals from the communicationpartner) from the antenna ANT are transmitted to the reception externalterminals Prp and Prn via the dc cutting external capacitors Crp and Crnor the like, which are processed appropriately as reception signals(rxinp and rxinn) by the reception block RXBK. On the other hand, whenthe semiconductor device NFCIC operates in the battery-less mode, inputpower supplied from the external reader/writer (RW) to the antenna ANTis transmitted as the power signals (tp and tm) to the externalterminals Ptp and Ptm. Using the power signals (tp and tm), therectifying section RECT generates power and, using the power, thereception block RXBK and the antenna driver section ADRV operate.Specifically, the reception block RXBK appropriately processes the inputsignals from the antenna ANT and thereby recognizes an instruction fromthe external reader/writer (RW). When the semiconductor device NFCICreturns a reply to the external reader/writer RW, the antenna driversection ADRV modulates the load between the external terminals Ptp andPtm and causes the external reader/writer RW to recognize a change inmagnetic field that has resultantly occurred in the antenna ANT. Notethat, when the semiconductor device NFCIC operates in the card mode, theoperation is the same as that in the battery-less mode described aboveexcept that the operating power of the reception block RXBK and theantenna driver section ADRV is replaced with battery power.

If such a configuration example is used, compared with the case wherethe configuration example of FIG. 23 described above is used, the numberof the external terminals can be reduced to achieve reductions in thesize and cost of the NFC chip (and a system to which it is applied). Inaddition, it is possible to reduce transmission power leakage in theantenna driver section ADRV during transmission in the RW mode and theleakage of the input power from the antenna ANT not to the rectifyingsection RECT, but to the antenna driver section ADRV in the battery-lessmode, as described with reference to FIG. 23.

A description will be given to the former transmission power leakage inthe antenna driver section ADRV. When a configuration example as shownin FIG. 23 is used, if external terminals Pvp and Pvn can be set into,e.g., a no-load state (open state) or the like, the transmission powerleakage (a loss in effective power) can be reduced. However, if theexternal terminals Pvp and Pvn are actually brought into the no-loadstate or the like, amplitudes at the external terminals Pvp and Pvn maybe excessively increased by, e.g., LC resonance of an external componentor the like to exceed the breakdown voltages of transistors. Therefore,it is actually necessary to limit the amplitudes using any resistanceload so that a loss undesirably occurs in effective power. In addition,in various external components present in paths from the externalterminals Ptp and Ptm to the external terminals Pvp and Pvn, resistivecomponents actual exist, which may also cause a loss in effective power.

To prevent this, if the transmission (antenna driving) externalterminals Ptp and Ptm are used also as rectification external terminalsas in the configuration example of FIG. 1, during a RW mode period,e.g., the rectifying section RECT is brought into the OFF state to allowa reduction in transmission power leakage (a loss in effective power).That is, during the RW mode period, the potential at each of theexternal terminals Ptp and Ptm is driven by an internal circuit to beset to a power supply voltage or ground voltage. Accordingly, thepotentials at the external terminals Ptp and Ptm are limited to therange from the ground power supply voltage to the power supply voltage.A rectified power supply generated by a rectifying circuit using a diodebridge cannot exceed an input amplitude in principle. Therefore, whenthe rectified power supply is opened, after a potential of a given levelis reached, a rectifying operation is no longer performed so that therectifying section RECT is turned OFF. At this time, with regard to thebreakdown voltages of the transistors, the antenna driver section ADRVgenerates transmission power to the external terminals Ptp and Ptmduring the RW mode period, as described above, so that the power supplyvoltage of the antenna driver section ADRV is not exceeded.

On the other hand, in the same manner as during the latter battery-lessmode period also, by controlling the antenna driver section ADRV into anOFF state, the rectifying section RECT can rectify the power inputted tothe antenna driving external terminals Ptp and Ptm with no loss.However, if the rectifying section RECT is only simply coupled to theexternal terminals Ptp and Ptm, large leakage power may occur in thetransmission block TXBK during the rectifying operation, as illustratedin FIG. 2. In the semiconductor device for wireless communicationaccording to the present embodiment, it is a main characteristic featurethereof to find the problem and take measures (details thereof will bedescribed later) against the problem.

<Example of Problem in Transmission Block>

FIGS. 2( a) to 2(c) are illustrative views showing, in the semiconductordevice for wireless communication of FIG. 1, the problem when therectifying section is simply coupled to the antenna driving externalterminals. FIG. 2( a) schematically shows the state of a pull-up PMOStransistor in the antenna driver section ADRV during the battery-lessmode period. In this example, as shown in FIGS. 2( a) and 2(c), thepull-up PMOS transistor has been turned OFF at a power supply voltage(vccrf (e.g., 2.7 V)) generated by a full-wave rectifying circuit FWRCTin the rectifying section RECT. Since it is during the battery-less modeperiod, an external power supply voltage (txvcc) supplied from thebattery for antenna driving is 0 V. At this time, since the power supplyvoltage (vccrf) is obtained by rectifying the power signals (tp and tm),the potentials of the power signals (tp and tm) may exceed the powersupply voltage (vccrf), as shown in FIG. 2( c). In this case, thepull-up PMOS transistor operates using each of the signals (tp and tm)as a source and the external power supply voltage (txvcc) as a drain. Atthis time, if “tp (or tm)−vccrf>Vthp” is satisfied, a current reverselyflows from each of the signals (tp and tm) to the power supply voltage(txvcc) (=0 V) to inhibit the rectifying operation.

Also, as shown in FIG. 2( a), in the pull-up PMOS transistor, there is aparasitic PNP bipolar transistor using a p⁺-type diffusion layer (p⁺) asan emitter, an n-type well (nwell) as a base, and a p-type semiconductorsubstrate (psub) as a collector. To the p⁺-type diffusion layer (p⁺),the signals (tp and tm) are applied. To the p-type semiconductorsubstrate (psub), a ground power supply voltage (txvss) (=0 V) againstthe power supply voltage (txvcc) is applied. During a normal period, thepower supply voltage (vccrf), which is the highest potential, is appliedas the back bias (bulk voltage) of the pull-up PMOS transistor to ann-type well (nwell) without causing any problem. However, since “tp (ortm)−vccrf>0.6 V” may actually be satisfied as shown in FIG. 2( c), theparasitic PNP bipolar transistor is turned ON, and a current flows fromeach of the signals (tp and tm) to the ground power supply voltage(txvss) (=0 V), which has the potential of the p-type substrate (psub),to inhibit the rectifying operation.

As shown in FIG. 2( b), the same problem occurs also in a pull-down NMOStransistor in the antenna driver section ADRV. FIG. 2( b) schematicallyshows the state of the pull-down NMOS transistor in the antenna driversection ADRV during the battery-less mode period. In this example, thepull-down NMOS transistor has been turned OFF at the ground power supplyvoltage (txvss (=0 V)). In the current CMOS process, a triple wellstructure is fundamental. The p-type well (pwell) of the pull-down NMOStransistor is isolated by a deep n-type well (deep nwell) covering thep-type well (pwell) from the p-type semiconductor substrate (psub). Inthis case, in the pull-down NMOS transistor, there is a parasitic NPNbipolar transistor using an n⁺-type diffusion layer (n⁺) as an emitter,the p-type well (pwell) as a base, and the deep n-type well (deep well)as a collector.

To the n⁺-type diffusion layer (n⁺), the signals (tp and tm) areapplied. To the p-type well (pwell), the power supply voltage (txvss)(=0 V), which is the lowest potential, is applied as the back bias (bulkvoltage) of the pull-down NMOS transistor. In general, the deep n-typewell (deep nwell) is coupled to the power supply voltage (vccrf).However, as shown in FIG. 2( c), when the rectifying operation isperformed, the signals (tp and tm) may drop to a level of −0.6 V. As aresult, a large current flows to the collector of the parasitic NPNbipolar transistor to extract a current from the power supply voltage(vccrf).

Thus, when the rectifying section RECT is simply coupled to the antennadriving external terminals Ptp (signal tp) and Ptm (signal tm), duringthe battery-less mode period, leak paths are formed between the externalterminals Ptp and Ptm and the transistors in the antenna driver sectionADRV to inhibit the operation of the rectifying section RECT. Note that,when a configuration example as shown in, e.g., FIG. 23 is used, therectification external terminals (Pvn and Pvp) and the antenna drivingexternal terminals Ptp and Ptm are isolated from each other by externalcapacitors Cvp and Cvn or the like. Since the antenna driver section isnot directly coupled to the external terminals Pvn and Pvp, a problem asillustrated in FIG. 2 does not occur. However, in the configurationexample of FIG. 23, there is another problem as described above so thatit is desired to solve the problem of FIG. 2 in the configurationexample of FIG. 1.

<Schematic Configuration of NFC Chip (Main Portion)>

FIG. 3 is a circuit block diagram showing, in the semiconductor devicefor wireless communication of FIG. 1, an example of a detailedconfiguration of the main portion thereof, which is the configurationexample for solving the problem described with reference to FIG. 2. TheNFC chip NFCIC shown in FIG. 3 includes the rectifying section RECT, theantenna driver section ADRV, a rectification regulator driver RCTRGDRV,and a rectification regulator RECTREG in the transmission block TXBK.

The rectifying section RECT includes the full-wave rectifying circuitFWRCT, a voltage boosting circuit UPC, switches SW1 a and SW1 b, andcapacitors Cm and Cp. The full-wave rectifying circuit FWRCT performsfull-wave rectification of the power signals (tp and tm) inputted fromthe antenna ANT using the ground power supply voltage as a reference togenerate a power supply voltage (vccrect). The voltage boosting circuitUPC receives the power signals (tp and tm) described above via thecapacitors Cm and Cp and performs full-wave rectification thereof usingthe power supply voltage (vccrect) from the full-wave rectifying circuitFWRCT as a reference to generate a power supply voltage (vccrect2). Theturning ON/OFF of the switches SW1 a and SW1 b are complementarilycontrolled. In the battery-less mode, the power supply voltage (vccrect)is outputted as the power supply voltage (vccrf) and, otherwise (in thecard mode or RW mode), a power supply voltage (mvdd) from the battery isoutputted as the power supply voltage (vccrf).

The antenna driver section ADRV includes PMOS transistors MPup and MPum,NMOS transistors MNdp and MNdm, and switches SW2 a and SW2 b. The PMOStransistor MPup pulls up one terminal (external terminal Ptp) of theantenna ANT with the antenna driving power supply voltage (txvcc) fromthe battery, while the NMOS transistor MNdp pulls down the externalterminal Ptp with the antenna driving ground power supply voltage(txvss) from the battery. The PMOS transistor MPum pulls up the otherterminal (external terminal Ptm) of the antenna ANT with the powersupply voltage (txvcc), while the NMOS transistor MNdm pulls down theexternal terminal Ptm with the power supply voltage (txvss). Theswitches SW2 a and SW2 b complementarily operate and supply the boostedpower supply voltage (vccrect2) from the rectifying section RECT as theback bias (bulk voltage) of each of the PMOS transistors MPup and MPumduring the battery-less mode period or supply the power supply voltage(txvcc) as the back bias of each of the PMOS transistors MPup and MPumduring another mode period (card mode period or RW mode period).

The rectification regulator RECTREG includes an operational amplifiercircuit OPAMP10, and the rectification regulator driver RCTRGDRVincludes an NMOS transistor MNrg. The operational amplifier circuitOPAMP10 compares a resistance-divided voltage of the power supplyvoltage (vccrf) with a reference voltage (bgr08) and drives the gate ofthe NMOS transistor MNrg using the result of the comparison. The NMOStransistor MNrg has the source thereof coupled to the ground powersupply voltage and the drain thereof coupled to the power supply voltage(vccrect). Therefore, when the power supply voltage (vccrf) is higherthan a predetermined voltage (e.g., 2.7 V), the operational amplifiercircuit OPAMP10 lowers the power supply voltage (vccrect) via the NMOStransistor MNrg and resultantly lowers the power supply voltage (vccrf)via the switch SW1 b.

FIGS. 4( a) to 4(c) are illustrative views showing, in the semiconductordevice for wireless communication of FIG. 3, an example of operationthereof during the battery-less mode period. FIG. 4( a) schematicallyshows the state of the pull-up PMOS transistor (MPup or MPum) in theantenna driver section ADRV during the battery-less mode period. In thisexample, as shown in FIGS. 4( a) and 4(c), the pull-up PMOS transistorhas been turned OFF at the power supply voltage (vccrect2 (e.g., 5 V))generated by the voltage boosting circuit UPC in the rectifying sectionRECT. Since it is during the battery-less mode period, the externalpower supply voltage (txvcc) supplied for antenna driving from thebattery is 0 V. At this time, as shown in FIG. 2( c), the potentials ofthe power signals (tp and tm) may exceed the power supply voltage(vccrf) (=2.7 V) from the full-wave rectifying circuit FWRCT, but doesnot exceed the power supply voltage (vccrect2). As a result, unlike inthe case of FIG. 2( a), the pull-up PMOS transistor is not turned ON andtherefore it is possible to prevent the rectifying operation from beinginhibited.

Also, as shown in FIG. 4( a), in the pull-up PMOS transistor, there isthe parasitic PNP bipolar transistor using the p⁺-type diffusion layer(0 as the emitter, the n-type well (nwell) as the base, and the p-typesemiconductor substrate (psub) as the collector. To the p⁺-typediffusion layer (p⁺), the signals (tp and tm) are applied. To the p-typesemiconductor substrate (psub), the ground power supply voltage (txvss)(=0 V) against the power supply voltage (txvcc) is applied. Here, unlikein the case of FIG. 2( a), the n-type well (nwell) is supplied with theboosted power supply voltage (vccrect2 (e.g., 5 V)). In this case, thepotentials of the signals (tp and tm) each serving as the emitter do notexceed the potential of the power supply voltage (vccrect2) serving asthe base, and the parasitic PNP bipolar transistor retains the OFFstate. Therefore, it is possible to prevent the rectifying operationfrom being inhibited.

On the other hand, FIG. 4( b) schematically shows the state of thepull-down NMOS transistor (MNdp or MNdm) in the antenna driver sectionADRV. In this example, the pull-down NMOS transistor has been turned OFFat the ground power supply voltage (txvss (=0 V)). The pull-down NMOStransistor is formed to have the triple well structure, and the p-typewell (pwell) serving as a channel region is isolated from the p-typesemiconductor substrate (psub) by the deep n-type well (deepnwell)covering the p-type well (pwell). In this case, in the pull-down NMOStransistor, there is the parasitic NPN bipolar transistor using then⁺-type diffusion layer (n⁺) as the emitter, the p-type well (pwell) asthe base, and the deep n-type well (deep nwell) as the collector.

To the n⁺-type diffusion layer (n⁺), the signals (tp and tm) areapplied. To the p-type well (pwell), the ground power supply voltage(txvss) (=0 V), which is the lowest potential, is applied as the backbias (bulk voltage) of the pull-down NMOS transistor. Here, unlike inthe case of FIG. 2( b), the deep n-type well (deep nwell) is suppliedwith the ground power supply voltage (txvss (=0 V)). Therefore, as shownin FIG. 4( c), even when the signals (tp and tm) drop to a level ofabout −0.6 V while the rectifying operation is performed, the collectorof the parasitic NPN bipolar transistor is at 0 V. Accordingly, there isno flow of a large current and no extraction of a current from the powersupply voltage (vccrf) so that it is possible to prevent the rectifyingoperation from being inhibited. Note that, even when the deep n-typewell (deep nwell) is coupled to 0 V, if there is no PMOS transistor inthe deep n-type well, no particular problem arises.

Thus, by using the semiconductor device (NFC chip) for wirelesscommunication of each of FIGS. 1 and 3, it is possible to reduce leakagepower during the rectifying operation and a transmitting operation andachieve an improvement in power efficiency. Note that, in the antennadriver section ADRV of FIG. 3, the switches SW2 a and SW2 b are providedbecause, here, the power supply voltage (vccrect2) is fixed to a valuein the vicinity of 0 V when the rectifying operation is stopped in amode other than the battery-less mode. That is, at this time, a voltage(vccnwell) serving as the back bias and OFF voltage of the pull-up PMOStransistor is switched to the power supply voltage (txvcc) from thebattery.

In the configuration example of FIG. 3, by detecting the value of thepower supply voltage (vccrf) with the rectification regulator RECTREGand controlling the power supply voltage (vccrect) of the full-waverectifying circuit FWRCT with the rectification regulator driverRCTRGDRV, the value of the power supply voltage (vccrf) is indirectlycontrolled. This is because a low-pass filter effect due to theresistance of the switch SW1 b and an external capacitor C1 with respectto the power supply voltage (vccrf) allows easier power supply controlthan when the power supply voltage (vccrect) is directly controlled andconsequently allows stabilization of the power supply voltage (vccrf).That is, since a variation in power supply voltage (vccrf) is reduced bythe low-pass filter effect to be smaller than a variation in powersupply voltage (vccrect), selecting the power supply voltage (vccrf) asa control target consequently allows greater stabilization of the powersupply voltage (vccrf).

<Comparative Example of Pull-Up PMOS Transistor>

FIG. 24 is a circuit diagram showing an example of a configuration of apull-up PMOS transistor studied as a comparative example of FIG. 3. InFIG. 3, by controlling the back bias of each of the pull-up PMOStransistors MPup and MPum, power leakage during the rectifying operationis prevented. However, power leakage can also be prevented by providingeach of the pull-up PMOS transistors with a configuration as shown inFIG. 24. In FIG. 24, each of the pull-up PMOS transistors is formed oftwo series-coupled PMOS transistors and, through the coupling of theback biases of the two PMOS transistors to commonly coupled nodes, amaximum potential is supplied as the back bias. However, when such aconfiguration example is used, a gate length is doubled as a result ofthe series coupling so that, to ensure the same driving ability as thatof the pull-up PMOS transistor of FIG. 3, it is necessary to also doublea gate width. Consequently, a transistor area which is quadruple that inthe case of FIG. 1 s needed. In particular, since the pull-up PMOStransistors MPup and MPum of FIG. 3 and the like are for antennadriving, the sizes thereof are originally large, which is significantlydisadvantageous in a configuration example as shown in FIG. 24.

<Schematic Configuration of Mobile Phone System>

FIG. 5 is a block diagram showing an example of a configuration of amobile phone system to which the semiconductor device for wirelesscommunication according to the embodiment of the present invention isapplied. The mobile phone system shown in FIG. 5 includes a battery BAT,a power supply circuit VGEN, the NFC chip NFCIC, a short-distanceantenna ANT, a UIM chip UIM, a mobile communication RF processor RFIC, along-distance antenna ANTrf, a main processor CPU, a human interfaceHMIF, and the like. The power supply circuit VGEN is supplied with powerfrom the battery BAT or another external power supply and generatesvarious power supplies including an NFC power supply, a UIM powersupply, an RF power supply, and other power supplies. The mobilecommunication RF processor RFIC operates with the RF power supply toappropriately control communication between the main processor CPU andthe outside of the mobile phone system via a radio signal in a range of,e.g., several hundreds of megahertz to several gigahertz in theshort-distance antenna ANT. The human interface HMIF operates with thepower supply from the power supply circuit VGEN to perform various userprocesses such as, e.g., reporting information inputted from variousbuttons or the like to the main processor CPU or effecting predetermineddisplay on a display in accordance with information from the mainprocessor CPU.

The NFC chip NFCIC corresponds to the semiconductor device for wirelesscommunication according to the present embodiment. The NFC chip NFCICoperates with the NFC power supply from the power supply circuit VGEN inthe RW mode or card mode described above to appropriately controlcommunication between the main processor CPU and the outside of themobile phone system via, e.g., an electromagnetic field signal of 13.56MHz in the short-distance antenna ANT. On the other hand, in thebattery-less mode, the NFC chip NFCIC generates a power supply frompower inputted thereto from the short-distance antenna ANT and operatestherewith. Here, during a card mode period or a battery-less modeperiod, the NFC chip NFCIC performs predetermined communication with theUIM chip UIM (e.g., SIM card (Subscriber Identity Module Card)). At thistime, the NFC chip NFCIC needs to supply operating power toward the UIMchip UIM. Therefore, the NFC chip NFCIC supplies the UIM power from thepower supply circuit VGEN in the card mode, while supplying the powergenerated using the power inputted thereto from the short-distanceantenna ANT in the battery-less mode. Accordingly, in the battery-lessmode, rectification efficiency in the rectifying section RECT describedabove is particularly important so that the use of the NFC chipaccording to the present embodiment is useful.

<Detailed Configuration of (Entire) NFC Chip>

FIG. 6 is a block diagram showing an example of a more detailedconfiguration of the entire semiconductor device for wirelesscommunication of FIG. 1. The semiconductor device (NFC chip) NFCIC forwireless communication shown in FIG. 6 is formed over, e.g., onesemiconductor chip and includes the transmission block TXBK, a powersupply controller VCTL, the reception block RXBK, and various controlblocks which perform communication centered around the microprocessorMPU via the transmission block TXBK and the reception block RXBK andcontrol of the transmission block TXBK, the reception block RXBK, andthe power supply controller VCTL. To the microprocessor MPU, variousperipheral circuits are coupled via internal buses (not shown) or thelike. The various peripheral circuits include a volatile memory RAM, anonvolatile memory ROM, an EEPROM (Electrically Erasable andProgrammable Read Only Memory), a phase-locked loop circuit PLL, anoscillation circuit OSC, an external input/output circuit IO, asecurity-related circuit SECU, and the like.

The oscillation circuit OSC generates a reference clock signal based onan external crystal oscillator XTAL or the like. The phase-locked loopcircuit PLL generates an internal clock signal at a predeterminedfrequency using the reference clock signal. The external input/outputcircuit IO controls communication between the microprocessor MPU and theoutside via, e.g., a UART (Universal Asynchronous Receiver Transmitter),a SWP (Single Wire Protocol), a USB (Universal Serial Bus), or the like.Communication between the microprocessor MPU and the UIM chip (UIM) isperformed via SWP. The microprocessor MPU executes a predeterminedprogram (such as a control program for RW mode or a control program forIC card) using the RAM, the ROM, and the EEPROM and ensures securityusing the security-related circuit SECU in the process thereof.

The transmission block TXBK is supplied with the power supply voltages(for antenna driving (txvcc/txvss) and for the entire transmission block(mvdd/mvss)) generated from the battery and generates the antennadriving transmission signals (tp and tm), while performing communicationusing various signals with the microprocessor MPU. Also, thetransmission block TXBK rectifies the power signals (tp and tm) from anantenna (not shown) to generate the power supply voltages (vccrf andvccnwell) during the battery-less mode period, as described above. Thetransmission block TXBK is also supplied with power supply voltages(rxvcc/rxvss) for the reception block, the reference voltage (band gapvoltage) (bgr08) from a reference generating circuit REFG, a referencecurrent (tx_iref), and the like.

The reception block RXBK receives the reception signals (rxinp andrxinn) and a reception reference voltage (rxvmid) (common voltagebetween the reception signals (rxinp and rxinn)) each inputted theretofrom the antenna, demodulates the reception signals subjected to ASK(Amplitude shift keying) modulation, and outputs the demodulatedreception signals to the microprocessor MPU. At this time, the receptionblock RXBK also performs level control of the reference voltage(rxvmid), amplitude control of the reception signals, and the like. Thepower supply controller VCTL receives a SWP power supply voltage(swvccin) from the battery and supplies, in accordance with a controlsignal (swvccout_on) from the microprocessor MPU, a SWP power supplyvoltage (swvcout) toward a SWP device (i.e., UIM chip) coupled to theexternal input/output circuit IO. At this time, the power supplycontroller VCTL generates the SWP power supply voltage (swvccout) basedon the power supply voltages (vccrf and vccnwell) supplied from thetransmission block TXBK in the battery-less mode. In another mode, thepower supply controller VCTL generates the SWP power supply voltage(swvccout) based on the SWP power supply voltage (swvccin). Note that acontrol signal (swext) from the power supply controller VCTL is used as,e.g., an ON/OFF signal for an external switch or the like on such anoccasion as when the SWP power supply voltages (swvccin and swvccout)are coupled via the external switch. The power supply controller VCTLalso supplies the reception block power supply voltage (rxvcc) describedabove toward the transmission block TXBK.

In such a configuration, the transmission block TXBK performspredetermined operations in accordance with the RW mode, the card mode,and the battery-less mode each described above and also performs anoperation in an RF sensor mode (RFS mode), a clock extracting operation,and the like. The following is a brief description of the outline ofthese operations. First, in the RW mode, the transmission block TXBKreceives a control signal (carr_on) on a ‘H’ level from themicroprocessor MPU and drives the external antenna with a driving forceset by control signals (modp[5:0] and modn[5:0]) from the microprocessorMPU. At this time, through appropriate control of control signals(modp[5:0], modp2_(—)[5:0], and modn[5:0]) from the microprocessor MPU,the transmission block TXBK generates an ASK modulation signal. Thevalues of the control signals (modp[5:0], modp2_(—)[5:0], and modn[5:0])can be appropriately changed by a register circuit (not shown) providedin the microprocessor MPU. The transmission block TXBK outputs adetection signal (emer) in the case where, when the control signal(carr_on) is on the ‘H’ level, a high voltage (e.g., about txvcc+0.6 V)occurs in the transmission signal (tp/tm) (i.e., such as when an intensemagnetic field is inputted into a reverse current from the antenna or anoutput of the antenna).

Next, in the card mode, the transmission block TXBK performs a loadmodulating operation (i.e., a reply toward the external reader/writerRW) at an intensity set by the control signal (modn[5:0]) when a controlsignal (ld_on) from the microprocessor MPU is on the ‘H’ level.Subsequently, in the battery-less mode, the transmission block TXBKrectifies (and controls the voltages of) the power signals (tp and tm)from the antenna to generate the power supply voltage (vccrf) of, e.g.,2.7 V or the like and additionally boosts them to generate the powersupply voltage (vccnwell) of, e.g., about V. In the same manner as inthe card mode, the transmission block TXBK also performs the loadmodulating operation in accordance with the control signal (ld_on) fromthe microprocessor MPU. Furthermore, the transmission block TXBKdetermines that the battery-less mode is set (i.e., external power isnot supplied) and outputs a detection signal (bless).

Next, in the RFS mode, when the amplitudes of the reception signals(rxinp and rxinn) reach a given level or higher (i.e., when an input ofa carrier is detected), the transmission block TXBK causes a detectionsignal (cdet) to fall. Sensitivity on the detection of a carrier isprovided with a hysteresis characteristic. When the transmission blockTXBK has caused the detection signal (cdet) to fall, it holds the ‘L’level thereof for a period of, e.g., 100 to 500 μs. That is, the NFCchip according to the present embodiment is configured such that, in thecard mode or battery-less mode, circuit blocks other than that forperforming carrier detection are basically held in an inactive state forpower saving and the individual circuit blocks are activated in responseto carrier detection. Here, since ASK modulation has been performed, thedetected carrier has the hysteresis characteristic described above orthe function of retaining the level to prevent unneeded switching of thedetection signal (cdet). Subsequently, in the clock extractingoperation, the transmission block TXBK extracts the clock signal fromthe reception signal (rxinp). When the reception signal (rxinp) has noamplitude, the ‘L’ level is outputted.

<Detailed Configuration of (Entire) Transmission Block TXBK>

FIG. 7 is block diagram showing, in the semiconductor device forwireless communication of FIG. 6, an example of a detailed configurationof the transmission block TXBK thereof. In FIG. 7, the antenna driversection ADRV is a block which drives the external antenna with thetransmission signals (tp and tm) and includes the pull-up PMOStransistors, the pull-down NMOS transistors, and modulation percentcorrecting pull-down PMOS transistors. As described with reference toFIGS. 3 and 4, during the battery-less mode period, to prevent theparasitic PNP transistor of each of the pull-up PMOS transistors frominhibiting the rectifying operation, the antenna driver section ADRValso includes the switches for controlling the back bias. Also, duringthe RW mode period, the antenna driver section ADRV outputs thedetection signal (emer) when an abnormal voltage has occurred at theexternal terminals (in the transmission signals (tp and tm)).

Antenna driver driving sections ADRVCTLp and ADRVCTLm drive theindividual antenna driving MOS transistors in the antenna driver sectionADRV described above. At this time, the number of the MOS transistors tobe driven is controlled. In addition, to shape an output waveform fromthe antenna during the driving, a CR feedback circuit exists whichretards a change in the gate potential of each of the MOS transistors inthe antenna driver section ADRV. A transmission control section TXCTLmainly performs control of an antenna driving function. The transmissioncontrol section TXCTL also has the function of buffering a digital inputsignal. The rectifying section RECT rectifies a waveform inputtedthereto from the antenna to generate the power supply voltages. Therectifying section RECT also includes a 2-stage voltage boosting circuitfor generating the bulk voltage of each of the pull-up PMOS transistorsin the antenna driver section ADRV. The rectifying section RECT furtherhas the function of switching between the external power supply (mvdd)and the rectified power supply and the function of determining thebattery-less mode.

The rectification regulator RECTREG drives the rectification regulatordriver RCTRGDRV to control the magnitudes of the power supply voltagesgenerated in the rectifying section RECT. Before the rectified powersupply rises, the reference voltage (bgr08) from the referencegenerating circuit REFG of FIG. 6 does not rise so that the rectifiedpower supply is raised with a reference voltage (vref_vccrf) from aninternal current supply IREG. The rectification regulator driverRCTRGDRV receives an output from the rectification regulator RECTREG andextracts a current from the rectified power supply. The rectificationregulator driver RCTRGDRV also limits an amplitude at each of theexternal terminals (in each of the signals (tp and tm)) and maximallyextracts a current from the power supply voltage (vccrect) so as toprevent a reverse current flow from each of the external terminals(signals (tp and tm)).

A carrier detecting section TXCDET detects an amplitude that hasoccurred at the external terminal (reception signal rxinp or rxinn)during an RFS mode period. A detection signal is held for 100 to 500 μs.The detection of a carrier is not stopped even during another modeperiod. A clock extracting section CLKEXT extracts a clock from a signalinputted to the reception signal (rxinp) and outputs a clock signal(exclk1356). During a clock halt period, as the clock signal(exclk1356), the ‘L’ level is outputted. The internal current supplyIREG supplies the reference current to the rectification regulatorRECTREG and the carrier detecting section TXCDET. The internal currentsupply IREG also outputs, for the time when the rectified power supplyrises, a low-accuracy reference voltage using a difference between thethresholds Vth of the MOS transistors.

<Detailed Configuration of Antenna Driver Section ADRV>

FIG. 8 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of a detailed configuration of the antenna driversection ADRV thereof. The antenna driver section ADRV includes a TP/TMdriving section TPTMDV, a vccnwell generating section VCNWELG, and anemergency detecting section EMERDET. The TP/TM driving section TPTMDVincludes, for one of the external terminals (signal tp) as a drivingtarget, six pull-up PMOS transistors MPup_x, six pull-down NMOStransistors MNdp_x, and six modulation percent correcting pull-down PMOStransistors MPdp_x. Here, “x” has a value of 1, 2, 4, 8, 16, or 32 andeach of the MOS transistors has a driving force (i.e., transistor sizeratio) corresponding to the value. The six pull-up PMOS transistorsMPup_x are respectively driven by six drive signals (drv_pp[5:0]). Thesix pull-down NMOS transistors MNdp_x are respectively driven by sixdrive signals (drv_pn[5:0]). The six modulation percent correctingpull-down PMOS transistors MPdp_x are respectively driven by six drivesignals (drv_pp2[5:0]). By switching the operation/non-operation of eachof the drive signals, the driving forces of the pull-up PMOStransistors, the pull-down NMOS transistors, and the modulation percentcorrecting pull-down PMOS transistors can be adjusted to 64 stages.

Likewise, the TP/TM driving section TPTMDV includes, for the otherexternal terminal (signal tm) as a driving target, six pull-up PMOStransistors MPum_x, six pull-down NMOS transistors MNdm_x, and sixmodulation percent correcting pull-down PMOS transistors MPdm_x. The sixpull-up PMOS transistors MPum_x are respectively driven by six controlsignals (drv_mp[5:0]). The six pull-down NMOS transistors MNdm_x arerespectively driven by six control signals (drv_mn[5:0]). The sixmodulation percent correcting pull-down PMOS transistors MPdm_x arerespectively driven by six control signals (drv_mp2[5:0]). Here,detailed potentials at individual nodes in the pull-up PMOS transistorsMPup_x and MPum_x and the pull-down NMOS transistors MNdp_x and MNdm_xare as shown in FIGS. 3 and 4. The modulation percent correctingpull-down PMOS transistors MPdp_x and MPdm_x are used to restrict amodulation percent to the range of 8.5 to 13.5% against PVT (Process,Voltage, and Temperature) variations during ASK modulation based on a“Type B” standard. Control methods for the individual signals will bedescribed later.

In FIG. 8, the vccnwell generating section VCNWELG includes a crossswitch circuit CRSSW10, a selection switch circuit SELSW10, and threeinverter circuits IV10 to IV12. The cross switch circuit CRSSW10includes two PMOS transistors having series-coupled source/drainregions, and the commonly coupled nodes thereof are coupled to the powersupply voltage (vccnwell). As described above, the power supply voltage(vccnwell) is used for the gate voltage and bulk voltage of each of thepull-up PMOS transistors in the antenna driver section ADRV and thelike. A node other than that for the power supply voltage (vccnwell) inone of the two PMOS transistors in the cross switch circuit CRSSW10 iscross-coupled to the gate of the other transistor so that the boostedpower supply voltage (vccrect2) generated in the rectifying section RECTis compared with the external power supply voltage (txvcc) and the powersupply voltage at a higher potential is outputted as the power supplyvoltage (vccnwell). Note that the back-bias of each of the two PMOStransistors is coupled to the power supply voltage (vccnwell).

The selection switch circuit SELSW10 includes two series-coupled PMOStransistors, and the commonly coupled nodes thereof are coupled to thepower supply voltage (vccnwell), similarly to the cross switch circuitCRSSW10. The back bias of each of the two PMOS transistors is alsocoupled to the power supply voltage (vccnwell). The selection switchcircuit SELSW10 simply selects either the external power supply voltage(txvcc) or the boosted power supply voltage (vccrect2) in accordancewith the detection signal (bless) showing whether or not thebattery-less mode is set and supplies a correct potential to the powersupply voltage (vccnwell). At this time, the power supply potentials ofthe individual inverters IV10 to IV12 which drive the selection switchcircuit SELSW10 are adjusted appropriately. FIG. 9 is a supplementaryview of FIG. 8 and shows an example of potentials at the individualnodes in the vccnwell generating section VCNWELG.

Normally, during the battery-less mode period, the detection signalbless of 2.7 V is outputted. At this time, the required power supplyvoltage (vccnwell) is nearly equal to 5 V. To turn off the selectionswitch circuit SELSW10, a level shifter for achieving a shift from 2.7 Vto 5.0 V is required. However, in consideration of the actual operationthereof, the inverter circuits IV10 to IV12 that can be implemented withcircuits simpler than that of the level shifter are used instead. Theinverter IV10 inversely drives, e.g., the detection signal (bless) onthe ‘H’ level using the voltage (vccrf) as the power supply and outputs0 V. On receiving the output inputted thereto, the inverter IV11inversely drives the received output using the power supply voltage(vccnwell) and outputs a signal of, e.g., 5 V or the like. Normally,such a method does not result in successful operation of the selectionswitch circuit SELSW10 when the detection signal (bless) is on the ‘L’level. However, when the detection signal (bless) is on the ‘L’ level(i.e., during another mode period other than the battery-less modeperiod), vccnwell=txvcc=3.0 V is satisfied. In this case, when the ‘L’level of the detection signal (bless) is inverted in the inverter IV10which performs driving with the power supply voltage (vccrf), an outputpotential satisfies vccrf=mvdd−0.1=txvcc−0.2=2.8 V (lowest value). Whenthe potential of 2.8 V is inputted to the inverter IV11 which performsdriving with the power supply voltage (vccnwell), the ‘L’ level can beoutputted without any problem to allow the selection switch circuitSELSW10 to correctly operate.

Note that, in generating the power supply voltage (vccnwell), the twotypes of switch circuits (CRSSW10 and SELSW10) are provided for thefollowing purposes. First, the cross switch circuit CRSSW10 is providedfor the purpose of generating a correct potential for the power supplyvoltage (vccnwell) even if the power supply voltages (vccrf andvccrect2) have not completely risen for the reason of timing immediatelyafter the activation of the rectifying section RECT or the like and thedriving of the detection signal (bless) by the inverter circuits IV10 toIV12 using the voltages (vccrf and vccrect2) as the power supply isincomplete. In addition to the cross switch circuit CRSSW10, theselection switch circuit SELSW10 is provided for the purpose of ensuringhigher security since, if, e.g., the power supply voltages (vccrect2 andtxvcc) are at equal potentials for any reason, the PMOS transistors ofthe cross switch circuit CRSSW10 are each turned OFF.

In FIG. 8, the emergency detecting section EMERDET uses PMOS transistorsthe bulk voltage of each of which is the power supply voltage (vccnwell)so that the emergency detecting section EMERDET is provided in theantenna driver section ADRV. The emergency detecting section EMERDET isactivated via a NOR circuit NOR10 when the control signal (carr_on) ison the ‘H’ level and a control signal (emer_off) is on the ‘L’ level.When the emergency detecting section EMERDET has been activated, acurrent mirror circuit CM10 supplies a bias current of 20 μA to abiasing PMOS transistor MPm1 using iref_emer=10 μA from the clockextracting section CLKEXT (FIG. 7) and, resultantly, the gates of emerdetecting PMOS transistors MPm2 and MPm3 are biased.

Here, when the signals (tp and tm) exceed the voltage (txvcc), agate-source voltage Vgs of each of the transistors MPm2 and MPm3 exceedsthe gate-source voltage Vgs of the transistor MPm1 so that an excesscurrent over 20 μA flows into each of the transistors MPm2 and MPm3. Asa result, the potential of a signal (emer_sense) rises, an output of anAND circuit AD10 is inverted from the ‘L’ level to the ‘H’ level, andthe detection signal (emer) is outputted. Note that, when the emergencydetecting section EMERDET is not activated, the signal (emer_sense) isunstable but, since the ‘L’ level is inputted to one of the inputterminals of the AND circuit AD10, there is no problem.

<Detailed Configuration of Antenna Driver Driving Section ADRVCTL>

FIG. 10 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of a detailed configuration of the antenna driverdriving section ADRVCTL thereof. The antenna driver driving sectionsADRVCTLp and ADRVCTLm are circuits which drive the individual antennadriving MOS transistors (pull-up, pull-down, and modulation percentcorrecting MOS transistors) in the antenna driver section ADRV describedabove and control the number of the MOS transistors to be driven. InFIG. 10, six NAND circuits ND20_x operate using the voltage (vccnwell)as the power supply and output signals (drv_p2[0] to drv_p2[5]),respectively. Here, “x” has a value of 1, 2, 4, 8, 16, or 32 and thedriving force of each of the NAND circuits ND20_x is adjusted at a ratiocorresponding to the value. The signals (drv_p2[0] to drv_p2[5]) serveas drive signals for the modulation percent correcting pull-down PMOStransistors. Note that, based on the correlation between FIGS. 10 and 8,the signals (drv_p2[0] to drv_p2[5]) correspond to signals (drv_pp2[0]to drv_pp2[5]) of FIG. 8 when FIG. 10 shows the antenna driver drivingsection ADRVCTLp or signals (drv_mp2[0] to drv_mp2[5]) of FIG. 8 whenFIG. 10 shows the antenna driver driving section ADRVCTLm.

Likewise, six NAND circuits ND21_x operate using the voltage (vccnwell)as the power supply and output signals (drv_p[0] to drv_p[5]),respectively. The signals (drv_p[0] to drv_p[5]) serve as drive signalsfor the pull-up PMOS transistors. Also, six NOR circuits NR20_x operateusing the voltage (vccrf) as the power supply and output signals(drv_n[0] to drv_n[5]), respectively. The signals (drv_n[0] to drv_n[5])serve as drive signals for the pull-down NMOS transistors. Here, to eachof the drive signals directed toward the pull-up/pull-down MOStransistors, the CR feedback circuit for retarding a change in gatepotential for shaping an output waveform (specifically for reducing aharmonic component) has been added.

For example, the drive signals (drv_p[0] to drv_p[5]) for the pull-upPMOS transistors are commonly coupled via respective capacitors C10_x (xsatisfies x=1, 2, 4, 8, 16, or 32 and represents the ratio of acapacitive value), and the commonly coupled nodes thereof are coupled tothe signal (tp or tm) via a switch circuit MSW10 and a resistor R10.That is, the signal (tp or tm) is fed back to the signals (drv_p[0] todrv_p[5]) via a CR circuit. Note that, in the modulation percentcorrecting MOS transistors, a potential change is not particularlyretarded. The CR feedback circuit is turned OFF via switch circuits(MSW10 and MSW11) during a period other than a transmitting operationperiod in the RW mode to particularly prevent a situation such as theoccurrence of a leakage current during the rectifying operation due toerroneous driving of each of the antenna driving MOS transistors.

FIGS. 11( a) and 11(b) show an example of operation of the antennadriver driving section ADRVCTL of FIG. 10, of which FIG. 11( a) is awaveform chart during the RW mode period and FIG. 11( b) is a waveformchart during the card mode (battery-less mode) period. In FIG. 11( a),in the RW mode, the antenna driver driving section ADRVCTL drives theantenna mainly at 13.56 MHz to perform ASK modulation. During the RWmode period, vccnwell=txvcc≈vccrf is satisfied so that a mismatchbetween the power supply voltages does not present a problem. When thecontrol signal (carr_on) is on the ‘L’ level, signals (gate_pp=‘L’,gate_pn=vccrf, gate_mp=‘L’, and gate_mn=vccrf) are outputted from thetransmission control section TXCTL (FIG. 7). Therefore, each of thesignals (drv_pp2(mp2)[5:0]) has the voltage (vccnwell), each of thesignals (drv_pp(mp)[5:0]) has the voltage (vccnwell), and each of thesignals (drv_pn(mn)[5:0]) outputs the ‘L’ level. As a result, each ofthe MOS transistors in the antenna driver section ADRV is brought intoan OFF state and each of the signals (tp and tm) is brought into a highimpedance state.

On the other hand, when the ‘H’ level is inputted to the signal(carr_on), signals (gate_pp, gate_pn, gate_mp, and gate_mn) are inputtedas clocks at 13.56 MHz from the transmission control section TXCTL (FIG.7). At this time, the signals (gate_pp and gate_pn) are in the samephase and, likewise, the signals (gate_mp and gate_mn) are also in thesame phase. On the other hand, the signals (gate_pp and gate_mp orgate_pn and gate_mn) are in opposite phases. At this time, to signals(drv_pp(mp)[5:0]) each included in signals (modp_t[5:0]) from thetransmission control section TXCTL (FIG. 7) and corresponding to a bitto which the ‘H’ level is inputted, a clock is outputted, while signals(drv_pp(mp)[5:0]) each included in the signals (modp_t[5:0]) andcorresponding to a bit to which the ‘L’ level is inputted are each fixedto the voltage (vccnwell). Thus, according to the signals (modp[5:0])inputted from the microprocessor MPU of FIG. 6, the driving forces ofthe pull-up PMOS transistors are adjusted.

Likewise, to signals (drv_pp2(mp2)[5:0]) each included in signals(modp2_t[5:0]) from the transmission control section TXCTL andcorresponding to a bit to which the ‘H’ level is inputted, a clock isoutputted, while signals (drv_pp2(mp2)[5:0]) each included in thesignals (modp2_t[5:0]) and corresponding to a bit to which the ‘L’ levelis inputted are each fixed to the voltage (vccnwell). Thus, according tothe signals (modp2[5:0]) inputted from the microprocessor MPU, thedriving forces of the modulation percent correcting pull-down PMOStransistors can be adjusted. Also, to signals (drv_pn(mn)[5:0]) eachincluded in signals (modn_b[5:0]) from the transmission control sectionTXCTL and corresponding to a bit to which the ‘L’ level is inputted, aclock is outputted, while signals (drv_pn(mn)[5:0]) each included in thesignals (modn_b[5:0]) and corresponding to a bit to which the ‘H’ levelis inputted are each fixed to the ‘L’ level. Thus, according to thesignals (modn[5:0]) inputted from the microprocessor MPU, the drivingforces of the pull-down NMOS transistors are adjusted. Note that, when acarrier is outputted, the feedback circuit formed of the CR circuit isenabled and the waveforms of the signals (drv_pp(mp) and drv_pn(mn)) areobtuse. During other operations, the rectifying operation is inhibitedparticularly during the battery-less mode period so that the feedbackcircuit is in the OFF state.

In FIG. 11( b), in the card mode, the antenna driver driving sectionADRVCTL performs the load modulating operation mainly according to theload modulation control signal (ld_on). During the card mode period,vccnwell=txvcc≈vccrf is satisfied so that a mismatch between the powersupply voltages does not present a problem. When Ld_on=‘L’ is satisfied,in the same manner as when carr_on=‘L’ is satisfied during the RW modeperiod, the signals (gate_pp=‘L’, gate_pn=vccrf, gate_mp=‘L’, andgate_mn=vccrf) are outputted from the transmission control section TXCTL(FIG. 7). Therefore, each of the signals (drv_pp2(mp2)[5:0]) has thevoltage (vccnwell), each of the signals (drv_pp(mp)[5:0]) has thevoltage (vccnwell), and each of the signals (drv_pn(mn)[5:0]) is on the‘L’ level. As a result, each of the MOS transistors in the antennadriver section ADRV is brought into the OFF state and each of thesignals (tp and tm) is brought into the high-impedance state.

On the other hand, when the signal (ld_on=‘H’) is inputted from themicroprocessor MPU of FIG. 6, each of the signals (gate_pn and gate_mn)shifts to the ‘L’ level. Accordingly, to signals (drv_n[5:0]) eachincluded in the signals (modn_b[5:0]) and corresponding to a bit towhich the ‘L’ level has been inputted, the voltage (vccrf) is outputted,while signals (drv_n[5:0]) each included in the signals (modn_b[5:0])and corresponding to a bit to which the ‘H’ level has been inputted areeach fixed to the ‘L’ level. As a result, with the driving forcesaccording to the signals (modn[5:0]) inputted from the microprocessorMPU, the pull-down NMOS transistors of the antenna driver section ADRVare turned ON and the load modulating operation according to the signal(ld_on) is performed. At this time, since each of the signals (gate_ppand gate_mp) remains on the ‘L’ level irrespective of the signal(ld_on), each of the signals (drv_pp(mp)[5:0] and drv_pp2(mp2)[5:0]) isfixed to the voltage (vccnwell) so that the pull-up PMOS transistors andthe modulation percent correcting pull-down PMOS transistors in theantenna driver section ADRV remain in the OFF state.

In the battery-less mode, basically only the load modulating operationis performed so that the operation is not different from the operationduring the card mode period described above. The operation is differentonly in the settings of the power supply voltage, and vccnwell≈5 V issatisfied so that a mismatch between the power supply voltages occurs inregard to the amplitude of the input signal at the voltage (vccrf).However, as shown in FIG. 11( b), the level of each of the signals(gate_pp and gate_mp) is constantly fixed to satisfy gate_pp,gate_mp=‘L’ so that the signals present no problem in response to achange in power supply voltage. The signals (modp_t[5:0] andmodp2_t[5:0]) may be either on the ‘H’ level or the ‘L’ level but, aslong as gate_pp, gate_mp=‘L’ are satisfied, there is no flow of athrough current to the NAND circuits ND20_x and ND21_x (x=1, 2, 4, 8,16, or 32) so that no problem arises. However, it is safer, by way ofcaution, to set each of the signals (modp_t[5:0] and modp2_(—)[5:0]) tothe ‘L’ level.

<Detailed Configuration of Transmission Control Section TXCTL>

FIG. 12 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of a detailed configuration of the transmissioncontrol section TXCTL thereof. The transmission block TXBK receivesvarious control signals mainly from the microprocessor MPU of FIG. 6 andperforms control of the antenna driving function. The transmission blockTXBK also has the function of buffering a digital input signal. In FIG.12, when a signal (vmidpor or tx_stop) is on the ‘H’ level, thetransmission block TXBK does not perform the transmitting operation(tx_en=‘L’). On the other hand, when tx_en=‘H’ and carr_on=‘H’ aresatisfied, tx_en_modt_t=‘H’ is satisfied so that signals (rfclk1356 tand rfclk11356 b) are enabled and a clock is outputted to the signal(gate_pp(mn, mp, and pn)). The phases of the signals (rfclk1356 t andrfclk1356 b) are matched using a transfer gate TFG10, and the phases ofthe signals (gate_pp(mn, mp, and pn)) are also matched using transfergates TFG11 and TFG12.

When tx_en=‘L’ is satisfied, the signal (gate_pp(mp)) is fixed to the‘H’ level and the signal (gate_pn(mn)) is fixed to the ‘L’ level. Whentx_en_modt_t=‘H’ is satisfied, positive/negative pole signals (true/bar)are used appropriately such that clocks outputted to the signals(gate_pp and gate_pn) are in the same phase, clocks outputted to thesignals (gate_mp and gate_mn) are also in the same phase, and clocksoutputted to the signals (gate_pp and gate_mp) are in opposite phases.On the other hand, when tx_en=‘H’ and carr_on=‘L’ are satisfied,tx_en_modb_t=‘H’ is satisfied so that the signal (ld_on) is enabled andoutputted to the signal (gate_pn(mn)). At this time, the signal(gate_pp(mp)) is fixed to the ‘H’ level. The signals (modp2[5:0],modp[5:0], and modn[5:0]) are each buffered in consideration of thepositive/negative pole signals (true/bar) and outputted as the signals(modp2_t[5:0], modp_t[5:0], and modn_b[5:0]).

<Detailed Configuration of Rectifying Section RECT>

FIG. 13 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of a detailed configuration of the rectifying sectionRECT thereof. The rectifying section RECT includes a rectifying circuitRECTC, a power supply switching section PSWBK, and a battery-lessdetermining section BLSJG. The rectifying circuit RECTC is mainly formedof the first-stage full-wave rectifying circuit FWRCT which generatesthe power supply voltage (vccrect) as a rectified voltage output and thesecond-stage voltage boosting circuit UPC which generates the powersupply voltage (vccrect2) as a boosted voltage. The full-wave rectifyingcircuit FWRCT is formed of a diode bridge including four diode-coupledNMOS transistors.

The two input nodes of the diode bridge are coupled to the respectivesignals (tp and tm), while one of the two output nodes thereof iscoupled to the ground power supply voltage and, from the other of thetwo output nodes thereof, a signal obtained through full-waverectification of the signals (tp and tm) is outputted. During thebattery-less mode period, the signal from the output node is smoothedwith a MOS capacitor formed of an NMOS transistor MNc1 coupled betweenthe voltage (vccrect) and the ground power supply voltage so that thepower supply voltage (vccrect) is generated. Note that each of the NMOStransistors forming the diode bridge has low threshold voltagespecifications. On the other hand, during the card mode period and theRW mode period when a carrier is not outputted, the voltage (vccrect)from the full-wave rectifying circuit FWRCT is fixed to the ‘L’ level bythe functions of the rectification regulator RECTREG and therectification regulator driver RCTRGDRV, which will be described later.As a result, the rectifying circuit RECTC operates as a shunt circuitwhich limits the amplitudes of the signals (tp and tm).

The second-stage voltage boosting circuit UPC is formed of a diodebridge including four NMOS transistors having low threshold voltagespecifications, similarly to the full-wave rectifying circuit FWRCT,performs full-wave rectification of signals (tp_h and tm_h) inputtedfrom the signals (tp and tm) via the capacitors Cp and Cm, and storesthe output thereof in a capacitor formed of an NMOS transistor MNc2. Inthe voltage boosting circuit UPC, one of the two output nodes and oneterminal of the capacitor (MNc2) are coupled to the voltage (vccrect).This allows the voltage boosting circuit UPC to generate the powersupply voltage (vccrect2) one level higher than the voltage (vccrect).Note that the configuration including the full-wave rectifying circuitFWRCT, the voltage boosting circuit UPC, and the various capacitors (Cp,Cm, MNc1, and MNc2) can also be regarded as a configuration which drivesa Dickson-type charge pump circuit with both of the signals (true/bar).The voltage (vccrect2) is used as the bulk voltage of each of thepull-up PMOS transistors in the antenna driver section ADRV during thebattery-less mode period or the like.

Also, the rectifying circuit RECTC includes a limit circuit LMT forpreventing the voltage (vccrect2) from reaching a breakdown voltage. Thelimit circuit LMT limits the voltage (vccrect2) to a potentialcorresponding to two NMOS transistor stages from the voltage (vccrf).The rectifying circuit RECTC also includes a shunt NMOS transistorMNsh10 for also fixing the voltage (vccrect2) to the ‘L’ level when therectifying circuit RECTC operates as the shunt circuit, as describedabove. The shunt NMOS transistor MNsh10 extracts a current from thevoltage (vccrect2) to the ground power supply voltage whenshunt_drv_gate=‘H’ is satisfied.

The power supply switching section PSWBK generates the power supplyvoltage (vccrf). The power supply switching section PSWBK generates thepower supply voltage (vccrf) from the voltage (vccrect) in thebattery-less mode or from the external power supply voltage (mvdd) inanother mode other than the battery-less mode. The power supplyswitching section PSWBK includes selection switch circuits SELSW20 andSELSW21, a cross switch circuit CRSSW20, and an NMOS diode switchcircuit DNSW21. The selection switch circuit SELSW21 is a main switchincluding two series-coupled PMOS transistors, and the commonly couplednodes thereof are coupled to the voltage (vccrf). The selection switchcircuit SELSW21 controls one of the PMOS transistors into an ON statebased on the result of the determination by the battery-less determiningsection BLSJG and couples the voltage (vccrf) to the voltage (vccrect)or the voltage (mvdd).

Here, when the potential of the voltage (vccrf) is low, the battery-lessdetermining section BLSJG may not operate properly and the selectionswitch circuit SELSW21 may not be able to precisely operate. To preventthis (to cause the voltage (vccrf) to promptly rise), the NMOS diodeswitch circuit DNSW21 is provided. The NMOS diode switch circuit DNSW21includes two series-coupled NMOS transistors, and the commonly couplednodes thereof are coupled to the voltage (vccrf). Each of the NMOStransistors has low threshold voltage specifications and isdiode-coupled such that each of the vccrect side and mvdd side thereofserves as an anode. When the voltage (vccrf) approaches the potential ofthe voltage (vccrect) or the voltage (mvdd), the current driving forceof the NMOS diode switch circuit DNSW21 decreases but, around that time,the battery-less determining section BLSJG operates and the selectionswitch circuit SELSW21 operates so that there is no problem.

A further problem encountered in operating the selection switch circuitSELSW21 is the bulk (nwell) potential of the PMOS transistor in theselection switch circuit SELSW21. To solve the problem, in the samemanner as in the cross switch circuit CRSSW10 shown in FIG. 8, the crossswitch circuit CRSSW20 of FIG. 13 uses a higher one of the voltage(vccrect) and the voltage (mvdd) as a power supply voltage (hnwell_rect)and supplies the power supply voltage (hnwell_rect) to the bulk voltagein the selection switch circuit SELSW21. Furthermore, the selectionswitch circuit SELSW20 uses either the voltage (vccrect) or the voltage(mvdd) as the power supply voltage (hnwell_rect) and supplies the powersupply voltage (hnwell_rect) to the bulk voltage in the selection switchcircuit SELSW21.

The battery-less determining section BLSJG is formed of circuits eachusing the voltage (vccrf) as the power supply. The battery-lessdetermining section BLSJG checks the potential of the external powersupply voltage (mvdd) upon activation and determines whether or not thebattery-less mode is set. During the battery-less mode period, thevoltage (mvdd) should have fallen to the ‘L’ level and, when the voltage(mvdd) is on the ‘L’ level, it is determined from the logic threshold ofthe inverter circuit IV20 that the battery-less mode is set. The resultof the determination by the inverter circuit IV20 is latched by a latchcircuit LT10 through a shift of an inverted reset signal (rstb) to the‘H’ level and retained thereafter until the inverted reset signal (rstb)falls to the ‘L’ level. However, during the period since the invertercircuit IV20 determines that the battery-less mode is set until theinverted reset signal (rstb) rises, a leakage current may occursuccessively in the voltages (vccrect, vccrf, and mvdd) to invert theresult of the determination. Accordingly, an NMOS transistor MN10 whichis turned ON when it is determined that the battery-less mode is set isprovided to extract a weak current from the voltage (mvdd).

<Detailed Configuration of Rectification Regulator RECTREG andRectification Regulator Driver RCTRGDRV>

FIG. 14 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of detailed configurations of the rectificationregulator RECTREG and the rectification regulator driver RCTRGDRV. Therectification regulator RECTREG drives the rectification regulatordriver RCTRGDRV in order to control the value of the power supplyvoltage generated in the rectifying section RECT. The rectificationregulator driver RCTRGDRV receives an output from the rectificationregulator RECTREG and extracts a current from the rectified power supply(vccrect). Note that, before the rectified power supply rises, thereference voltage (bgr08) from the reference generating circuit REFG ofFIG. 6 does not rise. Therefore, the rectification regulator RECTREGraises the rectified power supply using the reference voltage(vref_vccrf) from the internal current supply IREG of FIG. 7.

Also, to limit the amplitudes at the external terminals (of the signals(tp and tm)) during the card mode period and prevent a reverse currentflow from each of the signals (tp and tm), the rectification regulatordriver RCTRGDRV maximally extracts a current from the voltage (vccrect).That is, during the card mode period, it is desired to maximally limitthe amplitudes at the transmission-system external terminals (of thesignals (tp and tm)) so as not to affect, e.g., a reception-systemoperation. However, if the amplitudes are excessively limited,transmission toward the external reader/writer RW becomes difficult.Therefore, here, the current is maximally extracted from the voltage(vccrect) to thereby cause the rectifying circuit RECTC of FIG. 13 tooperate as a shunt circuit and limit the amplitudes at the externalterminals (of the signals (tp and tm)) to a range of those of forwardvoltages in the diode bridge.

As shown in FIG. 14, the rectification regulator RECTREG is basically asimple shunt regulator including the operational amplifier circuitOPAMP10. The operational amplifier circuit OPAMP10 includes adifferential pair of PMOS transistors MP20 and MP21, a PMOS transistorMP23 serving as a tail current supply, NMOS transistors MN25 and MN26each serving as a load transistor, and the like. The operationalamplifier circuit OPAMP10 senses the power supply voltage (vccrf)thereof with a voltage dividing resistor including registers R20 to R22and compares the power supply voltage with the reference voltage (bgr08)(e.g., 800 mV) to generate a control signal (drv_gate). If the voltage(vccrf) has a potential higher than 2.7 V, the potential of the signal(drv_gate) becomes higher and, in response to this, the rectificationregulator driver RCTRGDRV extracts a larger amount of current from thepower supply voltage (vccrect) via the NMOS transistor MNrg toward theground power supply voltage (txvss). Conversely, if the voltage (vccrf)has a potential lower than 2.7 V, the potential of the signal (drv_gate)becomes lower and, in response to this, the rectification regulatordriver RCTRGDRV reduces the current extracted from the power supplyvoltage (vccrect) via the NMOS transistor MNrg.

Here, the reason for the extraction of the current from the voltage(vccrect), not directly from the voltage (vccrf) is that, as describedwith reference to FIG. 3, since a switch circuit (such as the selectionswitch circuit SELSW21 in the power supply switching section PSWBK ofFIG. 13) coupling the voltages (vccrect and vccrf) to each other has aresistance, even when input power from the antenna significantly variesdue to 100% ASK or the like, an amount of variation in voltage (vccrf)can be suppressed. The reason for the flow of the current not to thevoltage (mvss) (for the general transmission block), but to the voltage(txvss) (mainly for the antenna driver section) in the rectificationregulator driver RCTRGDRV is that, since it is necessary to cause acurrent of not less than 200 mA at a maximum to flow, the current shouldflow to a terminal (txvss) which is unlikely to affect another circuitand capable of allowing a large current to flow. Since the rectificationregulator RECTREG and the rectification regulator driver RCTRGDRV do nothave a current mirror configuration, even when the potentials of theground power supplies are different, no problem arises.

Also, as shown in FIG. 14, a MOS capacitor formed of an NMOS transistorMNcp is used for phase compensation to thereby achieve an areareduction. When FIG. 14 is viewed, it seems that dominant-polecompensation is performed but, when the signal (drv_gate) increases, acurrent extracted from the voltage (vccrect) increases and the voltage(vccrf) drops. Accordingly, drv_gate→vccrf involves a gain so thatmirror compensation is performed and the size of the MOS capacitor isminimized. Mirror compensation in a typical series regulator is likelyto allow introduction of RF noise from a power supply so that a PSRR(Power Supply Rejection Ratio) deteriorates. However, such aconfiguration results in successive occurrence of a drop in voltage(vccrect), a drop in signal (drv_gate) due to capacitor coupling, areduction in extracted current, and a rise in voltage (vccrf) and thusalso functions as a speed-up capacitor so that the power supply voltagerejection ratio PSRR is improved.

Furthermore, since the voltage (vccrf) and the signal (drv_gate) arecapacitor-coupled, even before the operational amplifier circuit OPAMP10is completely activated on a rising edge of the voltage (vccrf), it ispossible to raise the signal (drv_gate) and also suppress a rapid riseon the rising edge of the voltage (vccrf). Thus, using a phasecompensation capacitor, the rapid rise of the voltage (vccrf) can besuppressed but, on the contrary, the rise of the voltage (vccrf) tendsto slow. In particular, it is necessary to avoid a deadlock in which thevoltage (vccrf) is low, the operational amplifier circuit OPAMP10 is notactivated, the signal (drv_gate) does not operate, and the voltage(vccrf) remains low. Accordingly, the rectification regulator RECTREGincludes a start-up circuit including MOS transistors MN21 to MN23.

FIG. 15 is an illustrative view showing an example of operation of thestart-up circuit in the rectification regulator of FIG. 14. At thestart-up time, when power is inputted to the signals (tp and tm), thevoltage (vccrf) rises to be stabilized at a potential corresponding tothe current driving force of the rectification regulator driver RCTRGDRV(S150). At this time, the signal (drv_gate) is coupled to the voltage(vccrf) so that the potential thereof is substantially equal to that ofthe voltage (vccrf). At this time, since a current does not flow in theMOS transistor MN25 in the operational amplifier circuit OPAMP10irrespective of the presence or absence of the operation of theoperational amplifier circuit OPAMP10, a current does not flow also inthe start-up MOS transistor MN21 forming the current mirror circuittherewith. As a result, the gate of the start-up MOS transistor MN23remains capacitor-coupled to have a potential substantially equal tothat of the voltage (vccrf).

On the other hand, the internal current supply IREG of FIG. 7 isconfigured to be activated even with an extremely low voltage, as willbe described later in detail. Accordingly, the start-up MOS transistorMN22 current-mirrors a reference current (iref_vccrf_rfreg) from theinternal current supply IREG via a bias circuit BIAS10 to thereby allowa current to flow therein and extracts a current from the signal(drv_gate) through the start-up MOS transistor MN23. Through theextraction of the current from the signal (drv_gate), the potential ofthe signal (drv_gate) drops and the voltage (vccrf) begins to rise(S151). When the voltage (vccrf) has sufficiently risen and entered aregion where the control of the operational amplifier circuit OPAMP10 isperformed, a current flows to each of the MOS transistor MN25 and thestart-up MOS transistor MN21 in the operational amplifier circuitOPAMP10, and the current is extracted from the gate of the start-up MOStransistor MN23 (S152). After the gate voltage of the MOS transistorMN23 has sufficiently dropped, the start-up circuit is inactivated anddoes not interrupt the operation of the operational amplifier circuitOPAMP10.

In the NFC chip according to the present embodiment, after the voltage(vccrf) has risen, the reference voltage (bgr08) from the referencegenerating circuit REFG of FIG. 6 rises so that it is necessary to raisethe voltage (vccrf) in a state where there is no reference voltage.Therefore, the reference voltage (vref_vccrf) using a difference betweenthe thresholds Vth of the MOS transistors is generated in the internalcurrent supply IREG and, using the reference voltage (vref_vccrf), thevoltage (vccrf) is raised. In the state where a control signal (spor5 v)from the microprocessor MPU of FIG. 6 is on the ‘H’ level, thecomparison voltage of the operational amplifier circuit OPAMP10 is setto the voltage (vref_vccrf) by the selection circuit SEL10. Since thevoltage (vref_vccrf) is about 200 mV, the resistance-divided value canalso be simultaneously switched using the selection circuit SEL11.Thereafter, when the control signal (spor5 v) shifts to the ‘L’ level,the reference voltage (bgr08) is selected as the comparison voltage ofthe operational amplifier circuit OPAMP10 and the resistance-dividedvalue is switched, while the voltage (vccrf) is controlled using thevoltage (bgr08) as a reference.

As has been described with respect to the rectifying section RECT ofFIG. 13, during the card mode period or the RW mode period and when acarrier is not outputted, the voltage (vccrect) is fixed to the ‘L’level and the rectifying circuit RECTC operates as the shunt circuit forthe signals (tp and tm). Conversely, during the RW mode period and whena carrier is outputted, the voltage (vccrect) is brought into the highimpedance state to bring the rectifying circuit RECTC into the OFF stateas described with reference to FIG. 1 and not to inhibit the outputtingof the carrier (i.e., to prevent transmission power leakage).Accordingly, the rectification regulator RECTREG is configured toinclude a PMOS transistor MPpu for pulling up the signal (drv_gate) andan NMOS transistor MNpd for pulling down the signal (drv_gate) and,using a logic circuit section, appropriately switch the ON/OFF states ofthe MOS transistors. FIG. 16 is a truth table showing, in therectification regulator RECTREG of FIG. 14, an example of operation ofthe logic circuit section thereof.

In FIG. 16, when a control signal (txreg_off) from the microprocessorMPU of FIG. 6 is on the ‘H’ level, the operational amplifier circuitOPAMP10 stops its operation, and the signal (drv_gate) is pulled up.When txreg_off=‘L’ is satisfied and the detection signal (bless) fromthe battery-less determining section BLSJG of FIG. 13 is on the ‘H’level, the operational amplifier circuit OPAMP10 operates and the signal(drv_gate) is not pulled up/down. When txreg_off=‘L’ and bless=‘L’ aresatisfied and the control signal (carr_on) from the microprocessor MPUof FIG. 6 is on the ‘H’ level (i.e., when a carrier is outputted in theRW mode), the operational amplifier circuit OPAMP10 stops its operationand the signal (drv_gate) is pulled down. As a result, the voltage(vccrect) is brought into the high impedance state. When texreg_off=‘L’,bless=‘L’, and carr_on=‘L’ are satisfied (i.e., when a carrier is notoutputted in the card mode or the RW mode), the operational amplifiercircuit OPAMP10 stops its operation and the signal (drv_gate) is pulledup.

When the signal (drv_gate) is pulled up, a signal (shunt_drv_gate) is onthe ‘H’ level and the voltage (vccrect) is fixed to the ‘L’ level with astronger driving force in addition to the voltage (vccrf). That is, inthe rectification regulator driver RCTRGDRV, a shunt NMOS transistorMNsh20 is provided in parallel with the NMOS transistor MNrg and drivenwith the signal (shunt_drv_gate). This is because the regulators (therectification regulator RECTREG and the NMOS transistor MNrg in therectification regulator driver RCTRGDRV) have current driving forcescapable of controlling the voltage (vccrf) to satisfy Vccrf=2.7 V whenmaximum power is inputted on the assumption of a normal controloperation but, during a shunt operation, the voltage (vccrect) needs tobe further reduced to a lower potential. Note that, as shown in FIG. 13,when shunt_drv_gate=‘H’ is satisfied, in the rectifying circuit RECTC,the voltage (vccrect2) is also fixed to the ‘L’ level. When each of thevoltages (vccrect and vccrect2) is fixed to the ‘L’ level, each of thediode bridges in the rectifying circuit RECTC of FIG. 13 limits theamplitudes of the signals (tp and tm) to a range of those of forwardvoltages (threshold voltages of the diode-coupled MOS transistors)therein.

<Detailed Configuration of Clock Extracting Section CLKEXT>

FIG. 17 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of a detailed configuration of the clock extractingsection CLKEXT thereof. The clock extracting section CLKEXT is a circuitwhich extracts a clock from each of reception signals (rxinp and rxinn)inputted to reception-side external terminals in FIG. 6. In addition,during a clock halt period, the clock extracting section CLKEXT outputsthe ‘L’ level. Note that, in FIG. 17, preparatory elements are omitted.

The main body of the clock extracting section CLKEXT is a simplecomparator using an operational amplifier circuit OPAMP20. The twoinputs of the comparator (operational amplifier circuit OPAMP20) arereceived by PMOS transistors MP30 and MP31 so as to provide the clockextracting section CLKEXT with a configuration capable of receivinglow-voltage inputs because rxvmid=‘L’ is satisfied during thebattery-less mode period. One of the two inputs of the comparator has apotential higher than that of the voltage (rxvmid) by 25 mV, which isgenerated from a 10 μA current generated by current-mirroring thereference current (tx_iref) from the reference generating circuit REFGof FIG. 6 and a 2.5 kΩ resistance. The other of the two inputs of thecomparator is a signal obtained by removing a DC component from thesignal (rxinp) using the voltage (rxvmid) as a reference.

The comparator compares the two inputs with each other and outputs theclock signal (exclk1356) via an AND circuit AD20. Note that, when thesignal (rxinp) does not have an input amplitude, the 25 mV offsetmentioned above is added such that the ‘L’ level is outputted as theclock signal (exclk1356). The reason that a current (iref_emer) isoutputted by current-mirroring a current (tx_iref) is because thecurrent (tx_iref) is used in each of the clock extracting section CLKEXTand the emergency detecting section EMERDET in the antenna driversection ADRV shown in FIG. 8. Therefore, a bias circuit BIAS20 whichcurrent-mirrors the current (tx_iref) is stopped only when exclk_off=‘H’and emer_off=‘H’ are satisfied. When the control signal (spor5 v) isdisabled, the comparator is activated and, when the signal (vmidpor) isdisabled, the clock is outputted.

<Detailed Configuration of Carrier Detecting Section TXCDET>

FIGS. 18( a) and 18(b) show a detail of the carrier detecting sectionTXCDET in the transmission block TXBK of FIG. 7, of which FIG. 18( a) isa circuit diagram showing an example of a configuration thereof and FIG.18( b) is a waveform chart showing an example of operation in FIG. 18(a). The carrier detecting section TXCDET detects amplitudes occurring atthe reception external terminals (of the reception signals (rxinp andrxinn)) during the RFS mode period. The detected signals are retainedfor 100 to 500 μs.

Even during another mode period, carrier detection is not stopped. InFIG. 18( a), a reference current (iref_vccrf_cdet2) of, e.g., 20 nA isfirst inputted from the internal current supply IREG of FIG. 7 to bias adiode-coupled NMOS transistor MN40 to be biased. Since the flowingcurrent is small in amount, the gate-source voltage Vgs of the NMOStransistor MN40 is substantially the threshold Vth.

The reception signals (rxinp and rxinn) are inputted to two types ofrespective high-pass filters. First-type high-pass filters HPFpl andHPFnl have DC levels each set to a ground power supply voltage (rxvss)level. Second-type high-pass filters HPFph and HPFnh have DC levels eachset to a Vth level. To the high-pass filters HPFpl and HPFnl, thereception signals (rxinp and rxinn) are respectively inputted and, tothe high-pass filters HPFph and HPFnh also, the reception signals (rxinpand rxinn) are respectively inputted. Here, when an AC signal has notbeen inputted to either of the reception signals (rxinp and rxinn) (theDC level does not matter), signals (tp_ac_h and tm_ac_h) serving asoutput signals from the high-pass filters HPFph and HPFnh are on the Vthlevel, while signals (tp_ac and tm_ac) serving as output signals fromthe high-pass filters HPFpl and HPFnl are on the 0 V level.

A detection NMOS transistor MNcd1 has the source thereof coupled to thesignal (tm_ac) and the gate thereof coupled to the signal (tp_ac_h),while a detection signal NMOS transistor MNcd2 has the source thereofcoupled to the signal (tp_ac) and the gate thereof coupled to the signal(tm_ac_h). Accordingly, when an AC signal has not been inputted, thegate-source voltages of the NMOS transistors MNcd1 and MNcd2 aresubstantially biased to the threshold Vth. It may be said that, in thisstate, the MOS transistor MN40 to be biased and the detection MOStransistors MNcd1 and MNcd2 are in a current mirror configuration, and acurrent corresponding to a mirror ratio flows to each of the detectionMOS transistors MNcd1 and MNcd2 (set to about 4 nA). Note that alow-current current mirror has a large error but, since a state where acurrent scarcely flows is merely set in the circuit, a current mirrorerror does not present a problem.

Here, when AC signals are inputted to the reception signals (rxinp andrxinn), the AC signals are transmitted to the sources and gates of thedetection MOS transistors MNcd1 and MNcd2. Here, since the gates andsources of the MOS transistors MNcd1 and MNcd2 are coupled such that theAC signals in opposite phases are transmitted thereto, there is a momentwhere Vgs>Vth is satisfied in each of the MOS transistors MNcd andMNcd2. When a Vgs>Vth state is established, currents flow from the MOStransistors MNcd1 and MNcd2 and a comparison is made between the currentdriving forces of current comparison PMOS transistors MPr1 and MPr2 viaa signal (cdet_sense). As the amplitudes of the signals (rxinp andrxinn) increase, currents flowing in the detection MOS transistors MNcd1and MNcd2 increase and, when the increased currents exceed the currentvalues of the current comparison PMOS transistors MPr1 and MPr2, thedetection signal (cdet) shifts from the ‘H’ level to the ‘L’ level viaeach of the subsequent-stage circuits, and the input of a carrier isdetected.

When a carrier is not detected, by driving a PMOS transistor MPsw20coupled in series to the current comparison PMOS transistor MPr1 intothe ON state, each of the MOS transistors MPr1 and MPr2 is enabled sothat a larger current becomes a threshold. That is, settings have beenmade to detect a larger amplitude. On the other hand, when a carrier isdetected, only the PMOS transistor MPr2 is enabled, and settings havebeen made to detect a smaller amplitude. By switching between thecurrent comparison PMOS transistors MPr1 and MPr2, a carrier detectionamplitude is provided with a hysteresis. A node (sense_hold) having aplurality of PMOS transistors MPg coupled in series to a pull-up side ofan output stage thereof has been set to exert a large driving force fora shift from the ‘H’ level to the ‘L’ level and a small driving forcefor a shift from the ‘L’ level to the ‘H’ level. By the functions of thenode (sense_hold) and a MOS capacitor (MPc1) coupled thereto, thedetection signal (cdet) is configured to momentarily shift from the ‘H’level to the ‘L’ level, but hold the ‘L’ level for about 100 to 500 μsin a shift from the ‘L’ level to the ‘H’ level.

<Detailed Configuration of Internal Current Supply IREG>

FIG. 19 is a circuit diagram showing, in the transmission block TXBK ofFIG. 7, an example of a detailed configuration of the internal currentsupply IREG thereof. The internal current supply IREG is a circuit whichsupplies a current to each of the rectification regulator RECTREG andthe carrier detecting section TXCDET. The internal current supply IREGalso outputs a (low-accuracy) reference voltage using a differencebetween the thresholds Vth of MOS transistors for the rising time of therectified power supply. As shown in FIG. 19, a current supply circuitCSC serving as the main body of the internal current supply IREGgenerates various reference currents (iref_vccrf_cdet1,iref_vccrf_cdet2, and iref_vccrf_rfreg) using a fundamental Widlarcurrent mirror circuit WCM10. Here, at the time of activation, astart-up circuit STRC turns ON MOS transistors MPsu1 and MNsu1 added tothe Widlar current mirror circuit WCM10 to thereby prevent high-speedactivation and a current supply halt. A reference potential generatingcircuit VTHREFG allows the same current to flow to an NMOS transistorMNlv having low threshold voltage specifications and an NMOS transistorMNnl having standard threshold voltage specifications and outputs adifference between the thresholds Vth thereof as the reference voltage(vref_vccrf).

<Detailed Configuration of Power Supply Controller VCTL (Main Portion)>

FIG. 20 is a circuit diagram showing an example of a detailedconfiguration of a main portion of the power supply controller VCTL ofFIG. 6. As shown in FIG. 20, the power supply controller VCTL includes aSWP power supply switching section SWPPSW. As described with referenceto FIGS. 5 and 6, the SWP power supply switching section SWPPSW is acircuit for supplying the proper power supply voltage (swvccout) to theUIM chip. As described above, to cause the NFC chip to operate on amobile phone system, communication with the UIM chip UIM is needed forsecurity. Here, in implementing a battery-less operation, a power supplyto the UIM chip UIM during the battery-less operation presents aproblem. When power is supplied directly to the power supply terminal ofthe UIM chip UIM, power may reversely flow to the battery through theregulator. There may be used a method which prevents the reverse flowusing an external switch, but there is a demand to avoid difficulty incontrol without power and increased complexity of the mobile phonesystem. To prevent these, it is necessary to embed a power supply switchin the NFC chip and switch between a power supply from the mobile phonesystem and a rectified power supply during the battery-less mode period.At that time, the bulk voltage of the power supply switch presents aproblem.

FIG. 21 is a supplementary view of FIG. 20 and shows a state of the SWPpower supply voltage (swvccout) expected for inputted power supplies andsignals. In FIGS. 20 and 21, swvccin is a SWP power supply given fromthe mobile phone system, swvccout is a SWP power supply given to the UIMchip, and swregout is a SWP power supply generated based on the powersupply voltage (vccrf) generated in the rectifying section RECT of FIG.13. That is, as shown in FIG. 20, a step-down regulator circuit DWREGlowers the power supply voltage (vccrf) (=2.7 V or the like) to generatethe SWP power supply (swregout) of 1.8 V or the like. Here, the NFC chipof the present embodiment corresponds to a plurality of operation modesbased on SWP standards and operations in the individual modes are asfollows.

First, in a “Class B” mode, 3.0 V is inputted to the SWP power supply(swvccin), and the SWP power supply (swvccin) is outputted to the SWPpower supply (swvccout). In a “Class C” mode, 1.8 V is inputted to theSWP power supply (swvccin), and the SWP power supply (swvccin) isoutputted to the SWP power supply (swvccout). In a battery-less mode(BLESS), no power is supplied to the SWP power supply (swvccin) (0 V),and the SWP power supply (swregout) is outputted to the SWP power supply(swvccout). In a “Power Off” mode, no power supply is given to the powersupply voltage (vccrf) and to the SWP power supply (swregout) (0 V), andthe SWP power supply (swvccin) is outputted to the SWP power supply(swvccout).

To satisfy these specifications, the SWP power supply switching sectionSWPPSW includes a PMOS transistor MPsw11 for coupling the SWP powersupply (swvccout) to the SWP power supply (swregout), a PMOS transistorMPsw10 for coupling the SWP power supply (swvccout) to the SWP powersupply (swvccin), and an NMOS transistor MNsw10 for coupling the SWPpower supply (swvccout) to the ground power supply voltage. The turningON/OFF of each of the transistors is controlled appropriately inaccordance with the detection signal (bless) from the rectifying sectionRECT of FIG. 13 and the signal (swvccout_on) from the microprocessor MPUof FIG. 6. Note that, as shown in FIG. 21, the voltage value of the SWPpower supply (swvccin) is not less than that of the SWP power supply(swregout) so that the PMOS transistor MPsw10 has a driving abilityhigher than that of the PMOS transistor MPsw11. Also, the PMOStransistors MPsw10 and MPsw11 that are power supply switches haverelatively large sizes and, for the driving thereof, a multi-stageinverter circuit IVBK is provided.

In such power supply switches (MPsw10 and MPSw11), in the same manner asfor the pull-up PMOS transistors in the antenna driver section ADRVdescribed above, bulk voltages (nwell_swppsw) thereof need to beproperly controlled. For example, when the bulk voltage of the powersupply switch MPsw10 is coupled to the SWP power supply (swvccin), sinceswvccin=0 V is satisfied during the battery-less mode period, powerleakage from the SWP power supply (swvccout) to the SWP power supply(swvccin) occurs. Also, for example, when the bulk voltage of the powersupply switch MPsw11 is coupled to the SWP power supply (swregout),power leakage occurs when the SWP power supply (swvccout) outputs theSWP power supply (swvccin). Accordingly, an NMOS diode switch circuitDNSW30, a cross switch circuit CRSSW30, and a selection switch circuitSELSW30 are provided here. Each of the switch circuits has the sameconfiguration as that described with respect to the power supplyswitching section PSWBK of FIG. 13 or the like. Basically, thehigher-potential one of the SWP power supplies (swvccin and swregout) issupplied to the bulk voltage (nwell_swppsw). Otherwise, in thebattery-less mode, the SWP power supply (swregout) is supplied theretoand, in other modes, the SWP power supply (swvccin) is supplied thereto.

When the signal (swvccout_on) is on the ‘L’ level, the power supplytoward the UIM chip UIM is cut off and, in this case, the NMOStransistor MNsw10 is turned ON and each of the PMOS transistors MPsw10and MPsw11 is turned OFF. On the other hand, when the signal(swvccout_on) is on the ‘H’ level, the power supply toward the UIM chipUIM is performed so that the NMOS transistor MNsw10 is turned OFF andeither of the PMOS transistors MPsw10 and MPsw11 is turned ON dependingon the level of the detection signal (bless). At this time, according toits specifications, the NMOS transistor MNsw10 used for the SWP powersupply (swvccin) is turned ON when the control signal (swext) is on the‘L’ level. The signal (swext) is outputted to the outside of the NFCchip and, as shown in, e.g., FIG. 22, used to drive an external switchOSW coupled in parallel to the PMOS transistor MPsw10 outside the NFCchip.

In the NFC chip, during the battery-less mode period, a power supplyobtained by lowering power generated from the rectified power with theregulator needs to be given to the UIM chip UIM. Accordingly, the NFCchip is configured to give the power supply that has passed through theNFC chip once to the UIM chip UIM even in an operation mode other thanthe battery-less mode. However, since a switch inside the NFC chip has arelatively high resistance, the switch resistance can be reduced usingthe external switch OSW. As shown in FIG. 22, the external switch OSWneeds to perform the same operation as that of the PMOS transistorMPsw10. Therefore, in the configuration of the external switch OSW, itis desirable to use a PMOS transistor. In addition, since the powersupply from the SWP power supply (swvccin) is stopped in thebattery-less mode, the power supply reversely flows in a simple PMOSswitch. Therefore, it is necessary to provide a PMOS transistor as shownin FIG. 24 with a 2-stage configuration and prevent a reverse currentflow from the bulk.

The following is the summary of the main characteristic features of theNFC chip of the present embodiment described above.

(1) In the NFC chip of the present embodiment, in order to use oneterminal as each of the antenna driving terminal and the rectified powerinput terminal, the bulk voltage of each of the antenna driving PMOStransistors is coupled to a high voltage during the rectifyingoperation. The high voltage is generated using the 2-stage rectifyingcircuit (or Dickson-type charge pump circuit). That is, if one terminalis simply used as each of the antenna driving terminal and the rectifiedpower input terminal, the rectified power may flow out to the groundpower supply voltage through the parasitic PNP bipolar transistor of theantenna driving PMOS transistor. Accordingly, the bulk voltage of thePMOS transistor is coupled to the 2-stage boosted voltage to bring theparasitic PNP transistor into the OFF state and eliminate outflow of therectified power.

(2) Likewise, when a triple well process is used for each of the antennadriving NMOS transistors, a “deep nwell” layer is coupled to the groundpower supply voltage. That is, when the triple well process is used forthe NMOS transistor, a current may flow from the power supply to theantenna driving terminal through the parasitic NPN bipolar transistor.Accordingly, by setting the potential of the “deep nwell” layer to thatof the ground power supply voltage, there is no outflow of a currentfrom the power supply.

(3) The characteristic features (1) and (2) described above allow oneterminal to be used as each of the antenna driving terminal and therectified power input terminal. That is, since each of the antennadriving terminal and the rectified power input terminal is a terminalwhich allows high power to flow, if they are placed in parallel, areaand cost increase may occur to additionally cause power leakage.Therefore, by using one terminal as each of the antenna driving terminaland the rectified power input terminal, it is possible to reduce areaand cost and prevent power leakage.

(4) In the NFC chip of the present embodiment, in order not to interruptthe rectifying operation, the feedback CR circuit for reducing harmonicthat is feedback-coupled from the antenna driving terminal to the gateof each of the antenna driving MOS transistors is cut off during therectifying operation. That is, during the rectifying operation, thefeedback CR circuit drives the gate of each of the antenna driving MOStransistors, though only slightly, and the input power from the antennaleaks from the antenna driving MOS transistor, which may degraderectification efficiency. Therefore, by cutting off the feedback CRcircuit, the gate voltage of each of the antenna driving MOS transistorsno longer moves and prevents the rectifying operation from beinginhibited.

(5) In the NFC chip of the present embodiment, in order to switch thebulk voltage of each of the PMOS transistors, the power supply switchingsection including the switch is provided. The switch of the power supplyswitching section has challenges such as preventing a reverse flow evenin a power exhausted state, occupying a minimized area, reliablyoperating even in a low-voltage state at the starting time of therectifying operation. Therefore, in the power supply switching section,the bulk voltage of the PMOS transistor is switched to, e.g., either theexternal power supply (mvdd) or the rectified power supply (vccrect) toprevent the reverse flow of the current via the PMOS transistorirrespective of the ON/OFF state of the external power supply (mvdd).For example, there is no need to provide the PMOS transistor with a2-stage configuration as shown in FIG. 24, and an area reduction can beachieved.

As the switch of the power supply switching section, e.g., adiode-coupled NMOS switch is used to allow the output power supplyvoltage (vccrf) to reliably rise even when the signal (bless) showingwhether or not a battery-less operation is performed during alow-voltage period has not been determined. When the voltage (vccrf) hasrisen to a certain level and the signal (bless) has been determined, byusing the PMOS switch as a main switch and controlling the PMOS switchwith the signal (bless), it is possible to couple the power supply by areliable operation. When the PMOS switch is used, it is useful toadditionally use a cross-coupled PMOS switch. The cross-coupled PMOSswitch can output the higher one of the two types of power supplyvoltages. As a result, even when the signal (bless) has not beendetermined during the low-voltage period, it is possible to reliablyraise the output power supply voltage.

(6) In the NFC chip of the present embodiment, the ASK modulationpercent is controlled by the antenna driving pull-up PMOS transistors,the antenna driving pull-down NMOS transistors, and the modulationpercent correcting pull-down PMOS transistors and, using registersettings in the microprocessor MPU or the like, optimum settings can beselected for the configuration of the external antenna or the like. Forexample, when, e.g., an ASK amplitude is intended to decrease to 80%, itis not sufficient to simply reduce the current driving force of each ofthe antenna driving MOS transistors to 80%. The antenna current drivingforce and the ASK amplitude have a non-linear relationship therebetween,and the relationship varies from one antenna to another. Moreover, whenthe current driving force of the MOS transistor has been changed by thePVT variations, even when the change in current driving force is thesame, the ASK modulation percent changes undesirably.

Therefore, by allowing the pull-up PMOS transistors/pull-down NMOStransistors to be set with a register for the control of the ASKmodulation percent, it is possible to set an optimum change in currentdriving force associated with the ASK modulation irrespective of thetype of the antenna and obtain a stable ASK modulation percent. Also, byturning ON the modulation percent correcting pull-down PMOS transistors,the ASK amplitude can be reduced. That is, by reducing the number of thepull-up PMOS transistors/pull-down NMOS transistors to be turned ON, theASK amplitude is reduced. Accordingly, when the current driving force ofeach of the MOS transistors varies due to the PVT variations, the ASKmodulation percent varies in opposite directions in the pull-up PMOStransistors/pull-down NMOS transistors and in the modulation percentcorrecting pull-down PMOS transistors. Therefore, by appropriately usingthe modulation percent correcting pull-down PMOS transistors, it ispossible to obtain a stable ASK modulation percent despite the PVTvariations. However, since the effect of the modulation percentcorrecting pull-down PMOS transistors also differs from one antenna toanother, settings with a register are allowed to be made.

(7) The NFC chip of the present embodiment is configured such that thechip recognizes that the battery-less operation is performed from abattery-less mode determination signal and the entire chip shifts to alow power consumption operation mode to be capable of elongating acommunication distance in the battery-less mode. That is, since the NFCchip obtains power from the mobile phone system, compared with a typicalNFC-compatible IC card (which operates only with antenna power), the NFCchip can operate with higher power. However, on the contrary, when theNFC chip operates in the battery-less mode, high power is required sothat the communication distance thereof is extremely shortened comparedwith that of the IC card. Accordingly, it is desired to sense thebattery-less operation and cause a shift to the low power consumptionmode but, if the NFC chip is configured to, e.g., directly supplyrectified power to the external power supply, it becomes difficult forthe NFC chip to sense the battery-less mode. Therefore, by cutting offthe external power supply from the rectified power supply, the NFC chipcan sense its operation in the battery-less mode (in the battery-lessmode when the external power supply has lowered). This allows the entireNFC chip to operate in the low power consumption mode and elongate thecommunication distance, though it is not so long as the communicationdistance of the IC card.

(8) The NFC chip of the present embodiment includes the carrierdetecting section which detects a carrier inputted from the outside. Thecarrier detecting section is configured to be able to obtain stablecarrier sensitivity by correcting the thresholds Vth of the MOStransistors using the high-pass filters irrespective of variations inthe thresholds Vth of the MOS transistors. The carrier detecting sectionoperates even when the NFC chip is in the RF sensor mode. The RF sensormode is a mode which monitors the presence or absence of a signal inputfrom the antenna and, at this time, the entire NFC chip except for thecarrier detecting section is in a standby state (power cut-off state).Accordingly, the power consumption of the carrier detecting section isassociated with the battery standby time of the mobile phone. Thisresults in the problem that it is difficult to use a complicated circuitand the threshold of carrier detection largely varies due to variationsin threshold Vth, temperature variations, or the like. Therefore, bycorrecting the threshold Vth of the MOS transistor using the high-passfilter, it is possible to monitor the carrier amplitude irrespective ofa change in threshold Vt and therefore implement a circuit configurationwhich is relatively resistant to the PVT variations.

(9) The NFC chip of the present embodiment includes the SWP power supplyswitching section, and the SWP power supply switching section isconfigured to appropriately switch the bulk voltage of each of the MOSswitches. In general, the power supply switch cannot recognize whetherthe input-side and output-side power supplies thereof are ON or OFF.When a switch having, e.g., a 1-stage configuration of a PMOS transistoris used as the power supply switch, a current reversely flows throughthe bulk. To prevent this, a configuration example as shown in FIG. 24described above can be used, but undesirably increases an area. Inparticular, since a large current flow and a low voltage drop arerequired of the power supply switch, it results in an extremely largeswitch. Accordingly, by appropriately switching the bulk voltage of theMOS switch, it is possible to prevent a reverse current flow through thebulk. As a result, the switch having the 1-stage configuration of thePMOS transistor can be used, and therefore the area can be reduced.

(10) The NFC chip of the present embodiment includes the SWP powersupply switching section and, in the SWP power supply switching section,the control signal for switching between the supply of power from themobile phone system to the UIM chip and the cur-off thereof shows thecut-off when it is on the ‘L’ level. If the control signal for switchingbetween the supply of power from the mobile phone system to the UIM chipand the cut-off thereof is set to show the cut-off when it is on the ‘H’level, when the mobile phone system is activated, it is undesirablyactivated with the power being supplied to the UIM chip. Therefore, bysetting the control signal for switching between the supply of powerfrom the mobile phone system to the UIM chip and the cut-off thereofsuch that the control signal shows the cut-off when it is on the ‘L’level, the power is not supplied to the UIM chip when the mobile phonesystem is activated and the sequence of system activation can becorrectly controlled.

While the invention achieved by the present inventors has beenspecifically described heretofore based on the embodiments thereof, thepresent invention is not limited to the foregoing embodiments. It willbe appreciated that various changes and modifications can be made in theinvention within the scope not departing from the gist thereof.

The semiconductor device for wireless communication according to thepresent embodiment is particularly useful when applied to a producthaving each of a reader/writer function and an IC card function but,needless to say, it is not limited thereto. For example, thesemiconductor device for wireless communication is similarly applicableto various general semiconductor devices for wireless communication suchas a product having each of a reader/writer function and a tag functionin RFID (Radio Frequency IDentification).

What is claimed is:
 1. A semiconductor device for wirelesscommunication, comprising: a first power supply voltage to which anexternal power supply is supplied; a second power supply voltage; afirst terminal for coupling to an antenna; a p-channel first MISFEThaving a source-drain path coupled between the first terminal and thefirst power supply voltage to drive the antenna; an n-channel secondMISFET having a source-drain path coupled between the first terminal andthe second power supply voltage to drive the antenna; and a rectifyingcircuit section coupled to the first terminal, wherein the rectifyingcircuit section uses an alternating current signal inputted to the firstterminal via the antenna to generate a third power supply voltage havinga value higher than that of the first power supply voltage and higherthan that of the high-potential voltage occurring at the first terminalwhen the alternating current signal has a maximum amplitude, and whereinthe third power supply voltage is used as a bulk voltage of the firstMISFET.
 2. A semiconductor device for wireless communication accordingto claim 1, wherein the first MISFET includes: a p-type firstsemiconductor layer; and an n-type second semiconductor layer which isformed in the first semiconductor layer and in which a channel of thefirst MISFET is formed, wherein the first semiconductor layer issupplied with a voltage level at the same potential as that of thesecond power supply voltage.
 3. A semiconductor device for wirelesscommunication according to claim 1, wherein the second MISFET includes:a p-type third semiconductor layer; an n-type fourth semiconductor layerformed in the third semiconductor layer; and a p-type fifthsemiconductor layer which is formed in the fourth semiconductor layerand in which a channel of the second MISFET is formed, wherein thefourth semiconductor layer is supplied with a voltage level at the samepotential as that of the second power supply voltage.
 4. A semiconductordevice for wireless communication according to claim 1, wherein thethird power supply voltage is used also as a gate voltage when the firstMISFET is driven to be turned OFF.
 5. A semiconductor device forwireless communication according to claim 1, wherein the rectifyingcircuit section includes: a first rectifying circuit which receives thealternating current signal inputted thereto to perform a rectifyingoperation via an element having a diode function; a first capacitorcoupled between an output node of the first rectifying circuit and aground power supply voltage; a second capacitor having one terminal towhich the alternating current signal is inputted; a second rectifyingcircuit which receives a signal from the other terminal of the secondcapacitor inputted thereto to perform a rectifying operation via anelement having a diode function; and a third capacitor coupled betweenan output node of the second rectifying circuit and the output node ofthe first rectifying circuit, wherein the third power supply voltage isgenerated from the output node of the second rectifying circuit, andwherein a fourth power supply voltage is generated from the output nodeof the first rectifying circuit.
 6. A semiconductor device for wirelesscommunication according to claim 5, further comprising: a first switchcircuit which selectively supplies either the third power supply voltageor the first power supply voltage as the bulk voltage of the firstMISFET.
 7. A semiconductor device for wireless communication accordingto claim 6, further comprising: a determining circuit which operatesusing the power supply voltage generated by the rectifying circuitsection to determine a magnitude of the external power supply, whereinthe first switch circuit has: a p-channel third MISFET having one ofsource/drain regions thereof coupled to the first power supply voltageand the other thereof coupled to the bulk voltage of the first MISFETsuch that an ON/OFF state thereof is controlled depending on a result ofthe determination by the determining circuit; and a p-channel fourthMISFET having one of source/drain regions thereof coupled to the thirdpower supply voltage and the other thereof coupled to the bulk voltageof the first MISFET such that an ON/OFF state thereof is controlledcomplementarily to the third MISFET depending on the result of thedetermination by the determining circuit.
 8. A semiconductor device forwireless communication according to claim 7, wherein the first switchcircuit further has: a p-channel fifth MISFET having one of source/drainregions thereof coupled to the first power supply voltage, the otherthereof coupled to the bulk voltage of the first MISFET, and a gateelectrode thereof coupled to the third power supply voltage; and ap-channel sixth MISFET having one of source/drain regions thereofcoupled to the third power supply voltage, the other thereof coupled tothe bulk voltage of the first MISFET, and a gate electrode thereofcoupled to the first power supply voltage.
 9. A semiconductor device forwireless communication according to claim 5, wherein, as the other ofthe external power supplies, each of a higher-potential fifth powersupply voltage and a lower-potential sixth power supply voltage isfurther supplied, the semiconductor device for wireless communicationfurther comprising: a second switch circuit which selectively supplieseither the fourth power supply voltage or the fifth power supply voltageas an internal power supply voltage.
 10. A semiconductor device forwireless communication according to claim 9, further comprising: aregulator circuit which controls a magnitude of the fourth power supplyvoltage, wherein the regulator circuit has: a seventh MISFET having asource-drain path coupled between the fourth power supply voltage andthe ground power supply voltage; and an amplifier circuit which detectsthe internal power supply voltage coupled to the fourth power supplyvoltage via the second switch circuit, compares the internal powersupply voltage with a preset reference voltage, and drives a gateelectrode of the seventh MISFET according to a result of the comparison.11. A semiconductor device for wireless communication according to claim5, further comprising: a second terminal which serves as a terminal forreceiving a modulation signal inputted from the antenna; a demodulatingcircuit for demodulating the modulation signal; and a shunt switch forshort-circuiting the output nodes of the first and second rectifyingcircuits to the ground power supply voltage.
 12. A semiconductor devicefor wireless communication according to claim 1, further comprising: afirst feedback path provided between the first terminal and a gateelectrode of the first MISFET to retard a shift of a gate voltage of thefirst MISFET using a resistive component and a capacitive component; anda second feedback path provided between the first terminal and a gateelectrode of the second MISFET to retard a shift of a gate voltage ofthe second MISFET using a resistive component and a capacitivecomponent, wherein the first feedback path includes a first couplingswitch for controlling conduction/non-conduction between the firstterminal and the gate electrode of the first MISFET, and wherein thesecond feedback path includes a second coupling switch for controllingconduction/non-conduction between the first terminal and the gateelectrode of the second MISFET.
 13. A semiconductor device for wirelesscommunication according to claim 1, wherein the first MISFET includes aplurality of MISFETs coupled in parallel to each other and havingdifferent driving abilities, wherein the second MISFET includes aplurality of MISFETs coupled in parallel to each other and havingdifferent driving abilities, wherein, when turning ON the first MISFET,the semiconductor device for wireless communication selects the MISFETto be actually turned ON from among the MISFETs included in the firstMISFET, and wherein, when turning ON the second MISFET, thesemiconductor device for wireless communication selects the MISFET to beactually turned ON from among the MISFETs included in the second MISFET.14. A semiconductor device for wireless communication according to claim13, further comprising: a p-channel eighth MISFET having a source-drainpath coupled between the first terminal and the second power supplyvoltage to drive the antenna, wherein the eighth MISFET includes aplurality of MISFETs coupled in parallel to each other and havingdifferent driving abilities, and wherein, when turning ON the eighthMISFET, the semiconductor device for wireless communication selects theMISFET to be actually turned ON from among the MISFETs included in theeighth MISFET.
 15. A semiconductor device for wireless communication,comprising: a first terminal to which a first power supply voltage issupplied as one of external power supplies and an alternating currentsignal inputted via an antenna is transmitted; a rectifying circuitsection coupled to the first terminal to rectify the alternating currentsignal and thereby generate a second power supply voltage; a regulatorcircuit which generates a third power supply voltage having apredetermined value from the second power supply voltage; a secondterminal serving as a terminal for supplying a direct current voltagetoward the outside; a p-channel first MISFET having a source-drain pathcoupled between the first power supply voltage and the second terminal;a p-channel second MISFET having a source-drain path coupled between thethird power supply voltage and the second terminal; and a switch circuitwhich selects either the first power supply voltage or the third powersupply voltage and outputs the selected power supply voltage as a fourthpower supply voltage, wherein the fourth power supply voltage issupplied to a bulk of each of the first and second MISFETs.
 16. Asemiconductor device for wireless communication according to claim 15,further comprising: a determining circuit which operates using thesecond power supply voltage generated by the rectifying circuit sectionto determine a magnitude of the external power supply, wherein theswitch circuit has; a p-channel third MISFET having one of source/drainregions thereof coupled to the first power supply voltage and the otherthereof coupled to the fourth power supply voltage such that an ON/OFFstate thereof is controlled depending on a result of the determinationby the determining circuit; and a p-channel fourth MISFET having one ofsource/drain regions thereof coupled to the third power supply voltageand the other thereof coupled to the fourth power supply voltage suchthat an ON/OFF state thereof is controlled complementarily to the thirdMISFET depending on the result of the determination by the determiningcircuit.
 17. A semiconductor device for wireless communication accordingto claim 16, wherein the switch circuit further has: a p-channel fifthMISFET having one of source/drain regions thereof coupled to the firstpower supply voltage, the other thereof coupled to the fourth powersupply voltage, and a gate electrode thereof coupled to the third powersupply voltage; and a p-channel sixth MISFET having one of source/drainregions thereof coupled to the third power supply voltage, the otherthereof coupled to the fourth power supply voltage, and a gate electrodethereof coupled to the first power supply voltage.
 18. A semiconductordevice for wireless communication according to claim 16, wherein theswitch circuit further has: an n-channel seventh MISFET having a drainregion and a gate electrode thereof each coupled to the first powersupply voltage and a source region thereof coupled to the fourth powersupply voltage; and an n-channel eighth MISFET having a drain region anda gate electrode thereof each coupled to the third power supply voltageand a source region thereof coupled to the fourth power supply voltage.